#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr  1 2019
#install: /usr/local/diamond/3.11_x64/synpbase
#OS: Linux 
#Hostname: pink

# Thu Nov 19 13:14:11 2020

#Implementation: usb3_plugin_impl


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: /usr/local/diamond/3.11_x64/synpbase
OS: Arch Linux
Hostname: pink

Implementation : usb3_plugin_impl
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:26:38

@N: :  | Running in 64-bit mode 

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: /usr/local/diamond/3.11_x64/synpbase
OS: Arch Linux
Hostname: pink

Implementation : usb3_plugin_impl
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:26:38

@N: :  | Running in 64-bit mode 
@I::"/usr/local/diamond/3.11_x64/synpbase/lib/lucent/machxo2.v" (library work)
@I::"/usr/local/diamond/3.11_x64/synpbase/lib/lucent/pmi_def.v" (library work)
@I::"/usr/local/diamond/3.11_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
@I::"/usr/local/diamond/3.11_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
@I::"/usr/local/diamond/3.11_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
@I::"/usr/local/diamond/3.11_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
@I::"/home/anuejn/code/apertus/nGateware/src/experiments/build/usb3_plugin_Usb3Plugin_JTAG__19_Nov_2020__13_12_36/usb3_plugin.v" (library work)
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module usb3_plugin
@N:CG364 : usb3_plugin.v(11736) | Synthesizing module plugin in library work.
Running optimization stage 1 on plugin .......
@N:CG364 : usb3_plugin.v(11761) | Synthesizing module plugin_ddr in library work.
Running optimization stage 1 on plugin_ddr .......
@N:CG364 : usb3_plugin.v(11786) | Synthesizing module plugin_in in library work.
Running optimization stage 1 on plugin_in .......
@N:CG364 : usb3_plugin.v(12102) | Synthesizing module sync in library work.
Running optimization stage 1 on sync .......
@N:CG364 : usb3_plugin.v(107) | Synthesizing module clocking in library work.
Running optimization stage 1 on clocking .......
@N:CG364 : usb3_plugin.v(243) | Synthesizing module counter in library work.
Running optimization stage 1 on counter .......
@N:CG364 : usb3_plugin.v(148) | Synthesizing module consume_buffered_cdc in library work.
Running optimization stage 1 on consume_buffered_cdc .......
@N:CG364 : usb3_plugin.v(178) | Synthesizing module consume_cdc in library work.
Running optimization stage 1 on consume_cdc .......
@N:CG364 : usb3_plugin.v(196) | Synthesizing module consume_dec in library work.
Running optimization stage 1 on consume_dec .......
@W:CL318 : usb3_plugin.v(209) | *Output o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@N:CG364 : usb3_plugin.v(235) | Synthesizing module consume_enc in library work.
Running optimization stage 1 on consume_enc .......
@N:CG364 : usb3_plugin.v(11812) | Synthesizing module produce_cdc in library work.
Running optimization stage 1 on produce_cdc .......
@N:CG364 : usb3_plugin.v(11830) | Synthesizing module produce_dec in library work.
Running optimization stage 1 on produce_dec .......
@W:CL318 : usb3_plugin.v(11843) | *Output o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@N:CG364 : usb3_plugin.v(11869) | Synthesizing module produce_enc in library work.
Running optimization stage 1 on produce_enc .......
@N:CG364 : usb3_plugin.v(11877) | Synthesizing module rst_cdc in library work.
Running optimization stage 1 on rst_cdc .......
@N:CG364 : usb3_plugin.v(11907) | Synthesizing module rst_dec in library work.
Running optimization stage 1 on rst_dec .......
@W:CL318 : usb3_plugin.v(11920) | *Output o has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@N:CG364 : usb3_plugin.v(12127) | Synthesizing module unbuffered in library work.
@W:CG532 : usb3_plugin.v(12198) | Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.
Running optimization stage 1 on unbuffered .......
@N:CL134 : usb3_plugin.v(14249) | Found RAM storage, depth=2048, width=32
@N:CG364 : usb3_plugin.v(359) | Synthesizing module fifo in library work.
Running optimization stage 1 on fifo .......
@W:CL169 : usb3_plugin.v(421) | Pruning unused register r_rst. Make sure that there are no unused intermediate registers.
@N:CG364 : usb3_plugin.v(52) | Synthesizing module cdc_fifo in library work.
Running optimization stage 1 on cdc_fifo .......
@N:CG364 : usb3_plugin.v(554) | Synthesizing module ft601$4 in library work.
Running optimization stage 1 on ft601$4 .......
@N:CG364 : usb3_plugin.v(499) | Synthesizing module ft601 in library work.
Running optimization stage 1 on ft601 .......
@N:CG364 : usb3_plugin.v(4) | Synthesizing module U$$0 in library work.
@W:CG146 : usb3_plugin.v(4) | Creating black box for empty module U$$0

Running optimization stage 1 on U$$0 .......
@N:CG364 : usb3_plugin.v(286) | Synthesizing module csr_bank in library work.
Running optimization stage 1 on csr_bank .......
@W:CL168 : usb3_plugin.v(287) | Removing instance U$$0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(618) | Synthesizing module ignore in library work.
Running optimization stage 1 on ignore .......
@W:CL168 : usb3_plugin.v(619) | Removing instance csr_bank because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(48) | Synthesizing module U$$0$7 in library work.
@W:CG146 : usb3_plugin.v(48) | Creating black box for empty module U$$0$7

Running optimization stage 1 on U$$0$7 .......
@N:CG364 : usb3_plugin.v(336) | Synthesizing module csr_bank$6 in library work.
Running optimization stage 1 on csr_bank$6 .......
@W:CL168 : usb3_plugin.v(337) | Removing instance U$$0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(668) | Synthesizing module ignore$5 in library work.
Running optimization stage 1 on ignore$5 .......
@W:CL168 : usb3_plugin.v(669) | Removing instance csr_bank because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(8) | Synthesizing module U$$0$10 in library work.
@W:CG146 : usb3_plugin.v(8) | Creating black box for empty module U$$0$10

Running optimization stage 1 on U$$0$10 .......
@N:CG364 : usb3_plugin.v(341) | Synthesizing module csr_bank$9 in library work.
Running optimization stage 1 on csr_bank$9 .......
@W:CL168 : usb3_plugin.v(342) | Removing instance U$$0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(673) | Synthesizing module ignore$8 in library work.
Running optimization stage 1 on ignore$8 .......
@W:CL168 : usb3_plugin.v(674) | Removing instance csr_bank because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(12) | Synthesizing module U$$0$13 in library work.
@W:CG146 : usb3_plugin.v(12) | Creating black box for empty module U$$0$13

Running optimization stage 1 on U$$0$13 .......
@N:CG364 : usb3_plugin.v(291) | Synthesizing module csr_bank$12 in library work.
Running optimization stage 1 on csr_bank$12 .......
@W:CL168 : usb3_plugin.v(292) | Removing instance U$$0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(623) | Synthesizing module ignore$11 in library work.
Running optimization stage 1 on ignore$11 .......
@W:CL168 : usb3_plugin.v(624) | Removing instance csr_bank because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(16) | Synthesizing module U$$0$16 in library work.
@W:CG146 : usb3_plugin.v(16) | Creating black box for empty module U$$0$16

Running optimization stage 1 on U$$0$16 .......
@N:CG364 : usb3_plugin.v(296) | Synthesizing module csr_bank$15 in library work.
Running optimization stage 1 on csr_bank$15 .......
@W:CL168 : usb3_plugin.v(297) | Removing instance U$$0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(628) | Synthesizing module ignore$14 in library work.
Running optimization stage 1 on ignore$14 .......
@W:CL168 : usb3_plugin.v(629) | Removing instance csr_bank because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(20) | Synthesizing module U$$0$19 in library work.
@W:CG146 : usb3_plugin.v(20) | Creating black box for empty module U$$0$19

Running optimization stage 1 on U$$0$19 .......
@N:CG364 : usb3_plugin.v(301) | Synthesizing module csr_bank$18 in library work.
Running optimization stage 1 on csr_bank$18 .......
@W:CL168 : usb3_plugin.v(302) | Removing instance U$$0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(633) | Synthesizing module ignore$17 in library work.
Running optimization stage 1 on ignore$17 .......
@W:CL168 : usb3_plugin.v(634) | Removing instance csr_bank because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(24) | Synthesizing module U$$0$22 in library work.
@W:CG146 : usb3_plugin.v(24) | Creating black box for empty module U$$0$22

Running optimization stage 1 on U$$0$22 .......
@N:CG364 : usb3_plugin.v(306) | Synthesizing module csr_bank$21 in library work.
Running optimization stage 1 on csr_bank$21 .......
@W:CL168 : usb3_plugin.v(307) | Removing instance U$$0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(638) | Synthesizing module ignore$20 in library work.
Running optimization stage 1 on ignore$20 .......
@W:CL168 : usb3_plugin.v(639) | Removing instance csr_bank because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(28) | Synthesizing module U$$0$25 in library work.
@W:CG146 : usb3_plugin.v(28) | Creating black box for empty module U$$0$25

Running optimization stage 1 on U$$0$25 .......
@N:CG364 : usb3_plugin.v(311) | Synthesizing module csr_bank$24 in library work.
Running optimization stage 1 on csr_bank$24 .......
@W:CL168 : usb3_plugin.v(312) | Removing instance U$$0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(643) | Synthesizing module ignore$23 in library work.
Running optimization stage 1 on ignore$23 .......
@W:CL168 : usb3_plugin.v(644) | Removing instance csr_bank because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(32) | Synthesizing module U$$0$28 in library work.
@W:CG146 : usb3_plugin.v(32) | Creating black box for empty module U$$0$28

Running optimization stage 1 on U$$0$28 .......
@N:CG364 : usb3_plugin.v(316) | Synthesizing module csr_bank$27 in library work.
Running optimization stage 1 on csr_bank$27 .......
@W:CL168 : usb3_plugin.v(317) | Removing instance U$$0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(648) | Synthesizing module ignore$26 in library work.
Running optimization stage 1 on ignore$26 .......
@W:CL168 : usb3_plugin.v(649) | Removing instance csr_bank because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(36) | Synthesizing module U$$0$31 in library work.
@W:CG146 : usb3_plugin.v(36) | Creating black box for empty module U$$0$31

Running optimization stage 1 on U$$0$31 .......
@N:CG364 : usb3_plugin.v(321) | Synthesizing module csr_bank$30 in library work.
Running optimization stage 1 on csr_bank$30 .......
@W:CL168 : usb3_plugin.v(322) | Removing instance U$$0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(653) | Synthesizing module ignore$29 in library work.
Running optimization stage 1 on ignore$29 .......
@W:CL168 : usb3_plugin.v(654) | Removing instance csr_bank because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(40) | Synthesizing module U$$0$34 in library work.
@W:CG146 : usb3_plugin.v(40) | Creating black box for empty module U$$0$34

Running optimization stage 1 on U$$0$34 .......
@N:CG364 : usb3_plugin.v(326) | Synthesizing module csr_bank$33 in library work.
Running optimization stage 1 on csr_bank$33 .......
@W:CL168 : usb3_plugin.v(327) | Removing instance U$$0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(658) | Synthesizing module ignore$32 in library work.
Running optimization stage 1 on ignore$32 .......
@W:CL168 : usb3_plugin.v(659) | Removing instance csr_bank because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(44) | Synthesizing module U$$0$37 in library work.
@W:CG146 : usb3_plugin.v(44) | Creating black box for empty module U$$0$37

Running optimization stage 1 on U$$0$37 .......
@N:CG364 : usb3_plugin.v(331) | Synthesizing module csr_bank$36 in library work.
Running optimization stage 1 on csr_bank$36 .......
@W:CL168 : usb3_plugin.v(332) | Removing instance U$$0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(663) | Synthesizing module ignore$35 in library work.
Running optimization stage 1 on ignore$35 .......
@W:CL168 : usb3_plugin.v(664) | Removing instance csr_bank because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : machxo2.v(1540) | Synthesizing module JTAGF in library work.
Running optimization stage 1 on JTAGF .......
@N:CG364 : usb3_plugin.v(774) | Synthesizing module jtag in library work.
@W:CG781 : usb3_plugin.v(789) | Input TCK on instance jtag_primitive is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(789) | Input TMS on instance jtag_primitive is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(789) | Input TDI on instance jtag_primitive is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(789) | Input JTDO2 on instance jtag_primitive is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
Running optimization stage 1 on jtag .......
@N:CG364 : usb3_plugin.v(807) | Synthesizing module jtag_controller in library work.
Running optimization stage 1 on jtag_controller .......
@N:CG364 : machxo2.v(82) | Synthesizing module BB in library work.
Running optimization stage 1 on BB .......
@N:CG364 : usb3_plugin.v(11168) | Synthesizing module pin_ft601_0__be in library work.
Running optimization stage 1 on pin_ft601_0__be .......
@N:CG364 : machxo2.v(498) | Synthesizing module IB in library work.
Running optimization stage 1 on IB .......
@N:CG364 : usb3_plugin.v(11207) | Synthesizing module pin_ft601_0__clk in library work.
Running optimization stage 1 on pin_ft601_0__clk .......
@N:CG364 : usb3_plugin.v(11216) | Synthesizing module pin_ft601_0__clk1 in library work.
Running optimization stage 1 on pin_ft601_0__clk1 .......
@W:CL168 : usb3_plugin.v(11219) | Removing instance ft601_0__clk1_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(11225) | Synthesizing module pin_ft601_0__data in library work.
Running optimization stage 1 on pin_ft601_0__data .......
@N:CG364 : usb3_plugin.v(11488) | Synthesizing module pin_ft601_0__gpio in library work.
Running optimization stage 1 on pin_ft601_0__gpio .......
@N:CG364 : machxo2.v(857) | Synthesizing module OB in library work.
Running optimization stage 1 on OB .......
@N:CG364 : usb3_plugin.v(11513) | Synthesizing module pin_ft601_0__oe in library work.
Running optimization stage 1 on pin_ft601_0__oe .......
@N:CG364 : usb3_plugin.v(11526) | Synthesizing module pin_ft601_0__read in library work.
Running optimization stage 1 on pin_ft601_0__read .......
@N:CG364 : usb3_plugin.v(11540) | Synthesizing module pin_ft601_0__reset in library work.
Running optimization stage 1 on pin_ft601_0__reset .......
@N:CG364 : usb3_plugin.v(11554) | Synthesizing module pin_ft601_0__rxf in library work.
Running optimization stage 1 on pin_ft601_0__rxf .......
@W:CL168 : usb3_plugin.v(11560) | Removing instance ft601_0__rxf_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(11567) | Synthesizing module pin_ft601_0__siwu in library work.
Running optimization stage 1 on pin_ft601_0__siwu .......
@N:CG364 : usb3_plugin.v(11581) | Synthesizing module pin_ft601_0__txe in library work.
Running optimization stage 1 on pin_ft601_0__txe .......
@N:CG364 : usb3_plugin.v(11594) | Synthesizing module pin_ft601_0__wakeup in library work.
Running optimization stage 1 on pin_ft601_0__wakeup .......
@N:CG364 : usb3_plugin.v(11619) | Synthesizing module pin_ft601_0__write in library work.
Running optimization stage 1 on pin_ft601_0__write .......
@N:CG364 : usb3_plugin.v(11632) | Synthesizing module pin_led_0 in library work.
Running optimization stage 1 on pin_led_0 .......
@N:CG364 : usb3_plugin.v(11641) | Synthesizing module pin_plugin_stream_input_0__clk_word in library work.
Running optimization stage 1 on pin_plugin_stream_input_0__clk_word .......
@N:CG364 : usb3_plugin.v(11650) | Synthesizing module pin_plugin_stream_input_0__lvds0 in library work.
Running optimization stage 1 on pin_plugin_stream_input_0__lvds0 .......
@N:CG364 : usb3_plugin.v(11659) | Synthesizing module pin_plugin_stream_input_0__lvds1 in library work.
Running optimization stage 1 on pin_plugin_stream_input_0__lvds1 .......
@N:CG364 : usb3_plugin.v(11668) | Synthesizing module pin_plugin_stream_input_0__lvds2 in library work.
Running optimization stage 1 on pin_plugin_stream_input_0__lvds2 .......
@N:CG364 : usb3_plugin.v(11677) | Synthesizing module pin_plugin_stream_input_0__lvds3 in library work.
Running optimization stage 1 on pin_plugin_stream_input_0__lvds3 .......
@N:CG364 : usb3_plugin.v(11686) | Synthesizing module pin_plugin_stream_input_0__valid in library work.
Running optimization stage 1 on pin_plugin_stream_input_0__valid .......
@N:CG364 : machxo2.v(1512) | Synthesizing module CLKDIVC in library work.
Running optimization stage 1 on CLKDIVC .......
@N:CG364 : usb3_plugin.v(93) | Synthesizing module clk_div_quater in library work.
@W:CG781 : usb3_plugin.v(100) | Input RST on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(100) | Input ALIGNWD on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
Running optimization stage 1 on clk_div_quater .......
@N:CG364 : machxo2.v(1525) | Synthesizing module ECLKSYNCA in library work.
Running optimization stage 1 on ECLKSYNCA .......
@N:CG364 : usb3_plugin.v(346) | Synthesizing module eclk_ddr in library work.
Running optimization stage 1 on eclk_ddr .......
@N:CG364 : machxo2.v(1676) | Synthesizing module DELAYD in library work.
Running optimization stage 1 on DELAYD .......
@N:CG364 : machxo2.v(1580) | Synthesizing module IDDRX4B in library work.
Running optimization stage 1 on IDDRX4B .......
@N:CG364 : usb3_plugin.v(678) | Synthesizing module iserdes in library work.
Running optimization stage 1 on iserdes .......
@W:CL168 : usb3_plugin.v(685) | Removing instance iddr because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(9788) | Synthesizing module lane0 in library work.
Running optimization stage 1 on lane0 .......
@W:CL168 : usb3_plugin.v(9918) | Removing instance iserdes because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(9909) | Removing instance delayd because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL169 : usb3_plugin.v(9907) | Pruning unused register last_captured_word[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : usb3_plugin.v(9903) | Pruning unused register start_current[4:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : usb3_plugin.v(9901) | Pruning unused register len_longest[4:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : usb3_plugin.v(9899) | Pruning unused register start_longest[4:0]. Make sure that there are no unused intermediate registers.
@N:CG364 : usb3_plugin.v(702) | Synthesizing module iserdes$1 in library work.
Running optimization stage 1 on iserdes$1 .......
@W:CL168 : usb3_plugin.v(709) | Removing instance iddr because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(10133) | Synthesizing module lane1 in library work.
Running optimization stage 1 on lane1 .......
@W:CL168 : usb3_plugin.v(10263) | Removing instance iserdes because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(10254) | Removing instance delayd because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL169 : usb3_plugin.v(10252) | Pruning unused register last_captured_word[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : usb3_plugin.v(10248) | Pruning unused register start_current[4:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : usb3_plugin.v(10246) | Pruning unused register len_longest[4:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : usb3_plugin.v(10244) | Pruning unused register start_longest[4:0]. Make sure that there are no unused intermediate registers.
@N:CG364 : usb3_plugin.v(726) | Synthesizing module iserdes$2 in library work.
Running optimization stage 1 on iserdes$2 .......
@W:CL168 : usb3_plugin.v(733) | Removing instance iddr because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(10478) | Synthesizing module lane2 in library work.
Running optimization stage 1 on lane2 .......
@W:CL168 : usb3_plugin.v(10608) | Removing instance iserdes because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(10599) | Removing instance delayd because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL169 : usb3_plugin.v(10597) | Pruning unused register last_captured_word[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : usb3_plugin.v(10593) | Pruning unused register start_current[4:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : usb3_plugin.v(10591) | Pruning unused register len_longest[4:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : usb3_plugin.v(10589) | Pruning unused register start_longest[4:0]. Make sure that there are no unused intermediate registers.
@N:CG364 : usb3_plugin.v(750) | Synthesizing module iserdes$3 in library work.
Running optimization stage 1 on iserdes$3 .......
@W:CL168 : usb3_plugin.v(757) | Removing instance iddr because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : usb3_plugin.v(10823) | Synthesizing module lane3 in library work.
Running optimization stage 1 on lane3 .......
@W:CL168 : usb3_plugin.v(10953) | Removing instance iserdes because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(10944) | Removing instance delayd because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL169 : usb3_plugin.v(10942) | Pruning unused register last_captured_word[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : usb3_plugin.v(10938) | Pruning unused register start_current[4:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : usb3_plugin.v(10936) | Pruning unused register len_longest[4:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : usb3_plugin.v(10934) | Pruning unused register start_longest[4:0]. Make sure that there are no unused intermediate registers.
@N:CG364 : machxo2.v(1730) | Synthesizing module EHXPLLJ in library work.
Running optimization stage 1 on EHXPLLJ .......
@N:CG364 : usb3_plugin.v(11695) | Synthesizing module pll in library work.
@W:CG781 : usb3_plugin.v(11723) | Input PHASESEL1 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PHASESEL0 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PHASEDIR on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PHASESTEP on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input LOADREG on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input STDBY on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLWAKESYNC on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input RESETM on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input RESETC on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input RESETD on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input ENCLKOP on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input ENCLKOS on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input ENCLKOS2 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input ENCLKOS3 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLCLK on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLRST on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLSTB on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLWE on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLDATI7 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLDATI6 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLDATI5 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLDATI4 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLDATI3 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLDATI2 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLDATI1 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLDATI0 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLADDR4 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLADDR3 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLADDR2 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLADDR1 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : usb3_plugin.v(11723) | Input PLLADDR0 on instance inst is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
Running optimization stage 1 on pll .......
@N:CG364 : usb3_plugin.v(11946) | Synthesizing module rx in library work.
Running optimization stage 1 on rx .......
@W:CL169 : usb3_plugin.v(12005) | Pruning unused register output__payload[31:0]. Make sure that there are no unused intermediate registers.
@N:CG364 : usb3_plugin.v(14414) | Synthesizing module usb3_plugin in library work.
@W:CG1226 : usb3_plugin.v(14533) | Found 0 port connections on instance ignore, expected 20. Please check the port map
@W:CG1226 : usb3_plugin.v(14535) | Found 0 port connections on instance ignore$19, expected 20. Please check the port map
@W:CG1226 : usb3_plugin.v(14537) | Found 0 port connections on instance ignore$20, expected 20. Please check the port map
@W:CG1226 : usb3_plugin.v(14539) | Found 0 port connections on instance ignore$21, expected 20. Please check the port map
@W:CG1226 : usb3_plugin.v(14541) | Found 0 port connections on instance ignore$22, expected 20. Please check the port map
@W:CG1226 : usb3_plugin.v(14543) | Found 0 port connections on instance ignore$23, expected 20. Please check the port map
@W:CG1226 : usb3_plugin.v(14545) | Found 0 port connections on instance ignore$24, expected 20. Please check the port map
@W:CG1226 : usb3_plugin.v(14547) | Found 0 port connections on instance ignore$25, expected 20. Please check the port map
@W:CG1226 : usb3_plugin.v(14549) | Found 0 port connections on instance ignore$26, expected 20. Please check the port map
@W:CG1226 : usb3_plugin.v(14551) | Found 0 port connections on instance ignore$27, expected 20. Please check the port map
@W:CG1226 : usb3_plugin.v(14553) | Found 0 port connections on instance ignore$28, expected 20. Please check the port map
@W:CG1226 : usb3_plugin.v(14555) | Found 0 port connections on instance ignore$29, expected 20. Please check the port map
Running optimization stage 1 on usb3_plugin .......
@W:CL168 : usb3_plugin.v(14619) | Removing instance pin_ft601_0__rxf because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(14598) | Removing instance pin_ft601_0__clk1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(14555) | Removing instance ignore$29 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(14553) | Removing instance ignore$28 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(14551) | Removing instance ignore$27 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(14549) | Removing instance ignore$26 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(14547) | Removing instance ignore$25 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(14545) | Removing instance ignore$24 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(14543) | Removing instance ignore$23 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(14541) | Removing instance ignore$22 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(14539) | Removing instance ignore$21 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(14537) | Removing instance ignore$20 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(14535) | Removing instance ignore$19 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : usb3_plugin.v(14533) | Removing instance ignore because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
Running optimization stage 2 on usb3_plugin .......
@N:CL159 : usb3_plugin.v(14442) | Input ft601_0__rxf__io is unused.
@N:CL159 : usb3_plugin.v(14435) | Input ft601_0__clk1__io is unused.
Running optimization stage 2 on rx .......
Running optimization stage 2 on pll .......
Running optimization stage 2 on EHXPLLJ .......
Running optimization stage 2 on lane3 .......
@W:CL138 : usb3_plugin.v(10930) | Removing register 'bit_aligned' because it is only assigned 0 or its original value.
@N:CL201 : usb3_plugin.v(10940) | Trying to extract state machine for register fsm_state.
Extracted state machine for register fsm_state
State machine has 2 reachable states with original encodings of:
   00
   01
@W:CL249 : usb3_plugin.v(10940) | Initial value is not supported on state machine fsm_state
@N:CL159 : usb3_plugin.v(10882) | Input plugin_ddr_clk is unused.
@N:CL159 : usb3_plugin.v(10884) | Input plugin_stream_input_0__lvds3__i is unused.
Running optimization stage 2 on iserdes$3 .......
@N:CL159 : usb3_plugin.v(754) | Input plugin_clk is unused.
@N:CL159 : usb3_plugin.v(755) | Input plugin_ddr_clk is unused.
@N:CL159 : usb3_plugin.v(751) | Input bitslip is unused.
@N:CL159 : usb3_plugin.v(752) | Input delayed is unused.
@N:CL159 : usb3_plugin.v(756) | Input plugin_rst is unused.
Running optimization stage 2 on lane2 .......
@W:CL138 : usb3_plugin.v(10585) | Removing register 'bit_aligned' because it is only assigned 0 or its original value.
@N:CL201 : usb3_plugin.v(10595) | Trying to extract state machine for register fsm_state.
Extracted state machine for register fsm_state
State machine has 2 reachable states with original encodings of:
   00
   01
@W:CL249 : usb3_plugin.v(10595) | Initial value is not supported on state machine fsm_state
@N:CL159 : usb3_plugin.v(10537) | Input plugin_ddr_clk is unused.
@N:CL159 : usb3_plugin.v(10539) | Input plugin_stream_input_0__lvds2__i is unused.
Running optimization stage 2 on iserdes$2 .......
@N:CL159 : usb3_plugin.v(730) | Input plugin_clk is unused.
@N:CL159 : usb3_plugin.v(731) | Input plugin_ddr_clk is unused.
@N:CL159 : usb3_plugin.v(727) | Input bitslip is unused.
@N:CL159 : usb3_plugin.v(728) | Input delayed is unused.
@N:CL159 : usb3_plugin.v(732) | Input plugin_rst is unused.
Running optimization stage 2 on lane1 .......
@W:CL138 : usb3_plugin.v(10240) | Removing register 'bit_aligned' because it is only assigned 0 or its original value.
@N:CL201 : usb3_plugin.v(10250) | Trying to extract state machine for register fsm_state.
Extracted state machine for register fsm_state
State machine has 2 reachable states with original encodings of:
   00
   01
@W:CL249 : usb3_plugin.v(10250) | Initial value is not supported on state machine fsm_state
@N:CL159 : usb3_plugin.v(10192) | Input plugin_ddr_clk is unused.
@N:CL159 : usb3_plugin.v(10194) | Input plugin_stream_input_0__lvds1__i is unused.
Running optimization stage 2 on iserdes$1 .......
@N:CL159 : usb3_plugin.v(706) | Input plugin_clk is unused.
@N:CL159 : usb3_plugin.v(707) | Input plugin_ddr_clk is unused.
@N:CL159 : usb3_plugin.v(703) | Input bitslip is unused.
@N:CL159 : usb3_plugin.v(704) | Input delayed is unused.
@N:CL159 : usb3_plugin.v(708) | Input plugin_rst is unused.
Running optimization stage 2 on lane0 .......
@W:CL138 : usb3_plugin.v(9895) | Removing register 'bit_aligned' because it is only assigned 0 or its original value.
@N:CL201 : usb3_plugin.v(9905) | Trying to extract state machine for register fsm_state.
Extracted state machine for register fsm_state
State machine has 2 reachable states with original encodings of:
   00
   01
@W:CL249 : usb3_plugin.v(9905) | Initial value is not supported on state machine fsm_state
@N:CL159 : usb3_plugin.v(9847) | Input plugin_ddr_clk is unused.
@N:CL159 : usb3_plugin.v(9849) | Input plugin_stream_input_0__lvds0__i is unused.
Running optimization stage 2 on iserdes .......
@N:CL159 : usb3_plugin.v(682) | Input plugin_clk is unused.
@N:CL159 : usb3_plugin.v(683) | Input plugin_ddr_clk is unused.
@N:CL159 : usb3_plugin.v(679) | Input bitslip is unused.
@N:CL159 : usb3_plugin.v(680) | Input delayed is unused.
@N:CL159 : usb3_plugin.v(684) | Input plugin_rst is unused.
Running optimization stage 2 on IDDRX4B .......
Running optimization stage 2 on DELAYD .......
Running optimization stage 2 on eclk_ddr .......
Running optimization stage 2 on ECLKSYNCA .......
Running optimization stage 2 on clk_div_quater .......
Running optimization stage 2 on CLKDIVC .......
Running optimization stage 2 on pin_plugin_stream_input_0__valid .......
Running optimization stage 2 on pin_plugin_stream_input_0__lvds3 .......
Running optimization stage 2 on pin_plugin_stream_input_0__lvds2 .......
Running optimization stage 2 on pin_plugin_stream_input_0__lvds1 .......
Running optimization stage 2 on pin_plugin_stream_input_0__lvds0 .......
Running optimization stage 2 on pin_plugin_stream_input_0__clk_word .......
Running optimization stage 2 on pin_led_0 .......
Running optimization stage 2 on pin_ft601_0__write .......
Running optimization stage 2 on pin_ft601_0__wakeup .......
Running optimization stage 2 on pin_ft601_0__txe .......
Running optimization stage 2 on pin_ft601_0__siwu .......
Running optimization stage 2 on pin_ft601_0__rxf .......
@N:CL159 : usb3_plugin.v(11558) | Input ft601_0__rxf__io is unused.
Running optimization stage 2 on pin_ft601_0__reset .......
Running optimization stage 2 on pin_ft601_0__read .......
Running optimization stage 2 on pin_ft601_0__oe .......
Running optimization stage 2 on OB .......
Running optimization stage 2 on pin_ft601_0__gpio .......
Running optimization stage 2 on pin_ft601_0__data .......
Running optimization stage 2 on pin_ft601_0__clk1 .......
@N:CL159 : usb3_plugin.v(11218) | Input ft601_0__clk1__io is unused.
Running optimization stage 2 on pin_ft601_0__clk .......
Running optimization stage 2 on IB .......
Running optimization stage 2 on pin_ft601_0__be .......
Running optimization stage 2 on BB .......
Running optimization stage 2 on jtag_controller .......
@N:CL201 : usb3_plugin.v(6514) | Trying to extract state machine for register fsm_state.
Running optimization stage 2 on jtag .......
Running optimization stage 2 on JTAGF .......
Running optimization stage 2 on ignore$35 .......
Running optimization stage 2 on csr_bank$36 .......
Running optimization stage 2 on U$$0$37 .......
Running optimization stage 2 on ignore$32 .......
Running optimization stage 2 on csr_bank$33 .......
Running optimization stage 2 on U$$0$34 .......
Running optimization stage 2 on ignore$29 .......
Running optimization stage 2 on csr_bank$30 .......
Running optimization stage 2 on U$$0$31 .......
Running optimization stage 2 on ignore$26 .......
Running optimization stage 2 on csr_bank$27 .......
Running optimization stage 2 on U$$0$28 .......
Running optimization stage 2 on ignore$23 .......
Running optimization stage 2 on csr_bank$24 .......
Running optimization stage 2 on U$$0$25 .......
Running optimization stage 2 on ignore$20 .......
Running optimization stage 2 on csr_bank$21 .......
Running optimization stage 2 on U$$0$22 .......
Running optimization stage 2 on ignore$17 .......
Running optimization stage 2 on csr_bank$18 .......
Running optimization stage 2 on U$$0$19 .......
Running optimization stage 2 on ignore$14 .......
Running optimization stage 2 on csr_bank$15 .......
Running optimization stage 2 on U$$0$16 .......
Running optimization stage 2 on ignore$11 .......
Running optimization stage 2 on csr_bank$12 .......
Running optimization stage 2 on U$$0$13 .......
Running optimization stage 2 on ignore$8 .......
Running optimization stage 2 on csr_bank$9 .......
Running optimization stage 2 on U$$0$10 .......
Running optimization stage 2 on ignore$5 .......
Running optimization stage 2 on csr_bank$6 .......
Running optimization stage 2 on U$$0$7 .......
Running optimization stage 2 on ignore .......
Running optimization stage 2 on csr_bank .......
Running optimization stage 2 on U$$0 .......
Running optimization stage 2 on ft601 .......
Running optimization stage 2 on ft601$4 .......
Running optimization stage 2 on cdc_fifo .......
Running optimization stage 2 on fifo .......
Running optimization stage 2 on unbuffered .......
Running optimization stage 2 on rst_dec .......
Running optimization stage 2 on rst_cdc .......
Running optimization stage 2 on produce_enc .......
Running optimization stage 2 on produce_dec .......
Running optimization stage 2 on produce_cdc .......
@N:CL159 : usb3_plugin.v(11816) | Input rst is unused.
Running optimization stage 2 on consume_enc .......
Running optimization stage 2 on consume_dec .......
Running optimization stage 2 on consume_cdc .......
@N:CL159 : usb3_plugin.v(182) | Input rst is unused.
Running optimization stage 2 on consume_buffered_cdc .......
Running optimization stage 2 on counter .......
Running optimization stage 2 on clocking .......
Running optimization stage 2 on sync .......
Running optimization stage 2 on plugin_in .......
Running optimization stage 2 on plugin_ddr .......
Running optimization stage 2 on plugin .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 77MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Nov 19 13:14:11 2020

###########################################################]

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: /usr/local/diamond/3.11_x64/synpbase
OS: Arch Linux
Hostname: pink

Implementation : usb3_plugin_impl
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:26:38

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 70MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Nov 19 13:14:11 2020

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  usb3_plugin_impl_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Nov 19 13:14:11 2020

###########################################################]



Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: /usr/local/diamond/3.11_x64/synpbase
OS: Arch Linux
Hostname: pink

Database state : /home/anuejn/code/apertus/nGateware/src/experiments/build/usb3_plugin_Usb3Plugin_JTAG__19_Nov_2020__13_12_36/usb3_plugin_impl/synwork/|usb3_plugin_impl
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr  1 2019 09:26:38

@N: :  | Running in 64-bit mode 
File /home/anuejn/code/apertus/nGateware/src/experiments/build/usb3_plugin_Usb3Plugin_JTAG__19_Nov_2020__13_12_36/usb3_plugin_impl/synwork/usb3_plugin_impl_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Nov 19 13:14:13 2020

###########################################################]


# Thu Nov 19 13:14:13 2020


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: /usr/local/diamond/3.11_x64/synpbase
OS: Arch Linux
Hostname: pink

Implementation : usb3_plugin_impl
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr  3 2019 09:24:52


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)

Reading constraint file: /home/anuejn/code/apertus/nGateware/src/experiments/build/usb3_plugin_Usb3Plugin_JTAG__19_Nov_2020__13_12_36/usb3_plugin.sdc
@N:MF284 :  | Setting synthesis effort to medium for the design 
Linked File:  usb3_plugin_impl_scck.rpt
Printing clock  summary report in "/home/anuejn/code/apertus/nGateware/src/experiments/build/usb3_plugin_Usb3Plugin_JTAG__19_Nov_2020__13_12_36/usb3_plugin_impl/usb3_plugin_impl_scck.rpt" file 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 106MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 106MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 116MB peak: 116MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 116MB peak: 118MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:MH105 :  | UMR3 is only supported for HAPS-80. 
@N:BN362 : usb3_plugin.v(14269) | Removing sequential instance r_rst (in view: work.unbuffered(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN115 : usb3_plugin.v(14644) | Removing instance pin_plugin_stream_input_0__lvds0 (in view: work.usb3_plugin(verilog)) of type view:work.pin_plugin_stream_input_0__lvds0(verilog) because it does not drive other instances.
@N:BN115 : usb3_plugin.v(14648) | Removing instance pin_plugin_stream_input_0__lvds1 (in view: work.usb3_plugin(verilog)) of type view:work.pin_plugin_stream_input_0__lvds1(verilog) because it does not drive other instances.
@N:BN115 : usb3_plugin.v(14652) | Removing instance pin_plugin_stream_input_0__lvds2 (in view: work.usb3_plugin(verilog)) of type view:work.pin_plugin_stream_input_0__lvds2(verilog) because it does not drive other instances.
@N:BN115 : usb3_plugin.v(14656) | Removing instance pin_plugin_stream_input_0__lvds3 (in view: work.usb3_plugin(verilog)) of type view:work.pin_plugin_stream_input_0__lvds3(verilog) because it does not drive other instances.
Encoding state machine fsm_state[1:0] (in view: work.lane0(verilog))
original code -> new code
   00 -> 0
   01 -> 1
@N:MO225 : usb3_plugin.v(9905) | There are no possible illegal states for state machine fsm_state[1:0] (in view: work.lane0(verilog)); safe FSM implementation is not required.
Encoding state machine fsm_state[1:0] (in view: work.lane1(verilog))
original code -> new code
   00 -> 0
   01 -> 1
@N:MO225 : usb3_plugin.v(10250) | There are no possible illegal states for state machine fsm_state[1:0] (in view: work.lane1(verilog)); safe FSM implementation is not required.
Encoding state machine fsm_state[1:0] (in view: work.lane2(verilog))
original code -> new code
   00 -> 0
   01 -> 1
@N:MO225 : usb3_plugin.v(10595) | There are no possible illegal states for state machine fsm_state[1:0] (in view: work.lane2(verilog)); safe FSM implementation is not required.
Encoding state machine fsm_state[1:0] (in view: work.lane3(verilog))
original code -> new code
   00 -> 0
   01 -> 1
@N:MO225 : usb3_plugin.v(10940) | There are no possible illegal states for state machine fsm_state[1:0] (in view: work.lane3(verilog)); safe FSM implementation is not required.
syn_allowed_resources : blockrams=8  set on top level netlist usb3_plugin

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 147MB)

@W:MT548 : usb3_plugin.sdc(4) | Source for clock clkop not found in netlist.
@W:MT548 : usb3_plugin.sdc(5) | Source for clock clock_signal not found in netlist.
@W:MT548 : usb3_plugin.sdc(6) | Source for clock jtck not found in netlist.


Clock Summary
******************

          Start                                        Requested     Requested     Clock        Clock                   Clock
Level     Clock                                        Frequency     Period        Type         Group                   Load 
-----------------------------------------------------------------------------------------------------------------------------
0 -       ft601_0__clk__io                             100.0 MHz     10.000        declared     default_clkgroup        298  
                                                                                                                             
0 -       plugin_stream_input_0__clk_word__p           50.0 MHz      20.000        declared     default_clkgroup        32   
                                                                                                                             
0 -       ft601_0__clk1__io                            100.0 MHz     10.000        declared     default_clkgroup        0    
                                                                                                                             
0 -       jtag|jtag_clk_inferred_clock                 100.0 MHz     10.000        inferred     Inferred_clkgroup_1     75   
                                                                                                                             
0 -       clk_div_quater|plugin_clk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     65   
                                                                                                                             
0 -       pll|plugin_ddr_clk_inferred_clock            100.0 MHz     10.000        inferred     Inferred_clkgroup_2     32   
=============================================================================================================================



Clock Load Summary
***********************

                                             Clock     Source                                              Clock Pin                               Non-clock Pin     Non-clock Pin                                                              
Clock                                        Load      Pin                                                 Seq Example                             Seq Example       Comb Example                                                               
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ft601_0__clk__io                             298       ft601_0__clk__io(port)                              ft601.ft601.in_transaction.C            -                 pin_ft601_0__clk.ft601_0__clk_0.I(IB)                                      
                                                                                                                                                                                                                                                
plugin_stream_input_0__clk_word__p           32        plugin_stream_input_0__clk_word__p(port)            clocking.plugin_in.counter[31:0].C      -                 pin_plugin_stream_input_0__clk_word.plugin_stream_input_0__clk_word_0.I(IB)
                                                                                                                                                                                                                                                
ft601_0__clk1__io                            0         ft601_0__clk1__io(port)                             -                                       -                 -                                                                          
                                                                                                                                                                                                                                                
jtag|jtag_clk_inferred_clock                 75        jtag_controller.jtag.jtag_primitive.JTCK(JTAGF)     jtag_controller.addr[31:0].C            -                 jtag_controller.un1_jtag_clk.I[0](inv)                                     
                                                                                                                                                                                                                                                
clk_div_quater|plugin_clk_inferred_clock     65        rx.clk_div_quater.inst.CDIVX(CLKDIVC)               rx.lane0_output__valid.C                -                 -                                                                          
                                                                                                                                                                                                                                                
pll|plugin_ddr_clk_inferred_clock            32        rx.pll.inst.CLKOS(EHXPLLJ)                          clocking.plugin_ddr.counter[31:0].C     -                 -                                                                          
================================================================================================================================================================================================================================================

@W:MT529 : usb3_plugin.v(11747) | Found inferred clock clk_div_quater|plugin_clk_inferred_clock which controls 65 sequential elements including clocking.plugin.counter[31:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : usb3_plugin.v(787) | Found inferred clock jtag|jtag_clk_inferred_clock which controls 75 sequential elements including jtag_controller.jtag.shift_tdi. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : usb3_plugin.v(11772) | Found inferred clock pll|plugin_ddr_clk_inferred_clock which controls 32 sequential elements including clocking.plugin_ddr.counter[31:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

2 non-gated/non-generated clock tree(s) driving 299 clock pin(s) of sequential element(s)
3 gated/generated clock tree(s) driving 172 clock pin(s) of sequential element(s)
0 instances converted, 172 sequential instances remain driven by gated/generated clocks

================================================================ Non-Gated/Non-Generated Clocks ================================================================
Clock Tree ID     Driving Element                                                             Drive Element Type     Fanout     Sample Instance                 
----------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId_0_3       pin_ft601_0__clk.ft601_0__clk_0.O                                           IB                     267        ft601.ft601.in_transaction      
ClockId_0_4       pin_plugin_stream_input_0__clk_word.plugin_stream_input_0__clk_word_0.O     IB                     32         clocking.plugin_in.counter[31:0]
================================================================================================================================================================
========================================================================= Gated/Generated Clocks =========================================================================
Clock Tree ID     Driving Element                              Drive Element Type     Unconverted Fanout     Sample Instance                       Explanation            
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId_0_1       rx.clk_div_quater.inst.CDIVX                 CLKDIVC                65                     rx.lane0_output__valid                Black box on clock path
ClockId_0_2       jtag_controller.jtag.jtag_primitive.JTCK     JTAGF                  75                     jtag_controller.jtag.shift_tdi        Black box on clock path
ClockId_0_5       rx.pll.inst.CLKOS                            EHXPLLJ                32                     clocking.plugin_ddr.counter[31:0]     Black box on clock path
==========================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 147MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 147MB)

None
None
@W:MF511 :  | Found issues with constraints. Please check constraint checker report "/home/anuejn/code/apertus/nGateware/src/experiments/build/usb3_plugin_Usb3Plugin_JTAG__19_Nov_2020__13_12_36/usb3_plugin_impl/usb3_plugin_impl_cck.rpt" . 

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 148MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 62MB peak: 148MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Nov 19 13:14:13 2020

###########################################################]


# Thu Nov 19 13:14:13 2020


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: /usr/local/diamond/3.11_x64/synpbase
OS: Arch Linux
Hostname: pink

Implementation : usb3_plugin_impl
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr  3 2019 09:24:52


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@N:MF284 :  | Setting synthesis effort to medium for the design 


Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)

@W:MO160 : usb3_plugin.v(9893) | Register bit word_aligned (in view view:work.lane0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : usb3_plugin.v(10238) | Register bit word_aligned (in view view:work.lane1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : usb3_plugin.v(10583) | Register bit word_aligned (in view view:work.lane2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : usb3_plugin.v(10928) | Register bit word_aligned (in view view:work.lane3(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.

Available hyper_sources - for debug and ip models
	None Found

@W:MO160 : usb3_plugin.v(10926) | Register bit rx.lane3.error (in view view:work.usb3_plugin(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : usb3_plugin.v(10581) | Register bit rx.lane2.error (in view view:work.usb3_plugin(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : usb3_plugin.v(10236) | Register bit rx.lane1.error (in view view:work.usb3_plugin(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : usb3_plugin.v(9891) | Register bit rx.lane0.error (in view view:work.usb3_plugin(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:BN132 : usb3_plugin.v(10940) | Removing sequential instance rx.lane3.fsm_state[0] because it is equivalent to instance rx.lane2.fsm_state[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : usb3_plugin.v(10595) | Removing sequential instance rx.lane2.fsm_state[0] because it is equivalent to instance rx.lane0.fsm_state[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : usb3_plugin.v(10940) | Removing user instance rx.lane3.fsm_state_1 because it is equivalent to instance rx.lane2.fsm_state_1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : usb3_plugin.v(10595) | Removing user instance rx.lane2.fsm_state_1 because it is equivalent to instance rx.lane0.fsm_state_1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : usb3_plugin.v(10940) | Removing user instance rx.lane3.fsm_state_ns[0] because it is equivalent to instance rx.lane2.fsm_state_ns[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : usb3_plugin.v(10595) | Removing user instance rx.lane2.fsm_state_ns[0] because it is equivalent to instance rx.lane0.fsm_state_ns[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : usb3_plugin.v(10940) | Removing user instance rx.lane3.fsm_state_srsts[0] because it is equivalent to instance rx.lane2.fsm_state_srsts[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : usb3_plugin.v(10595) | Removing user instance rx.lane2.fsm_state_srsts[0] because it is equivalent to instance rx.lane0.fsm_state_srsts[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : usb3_plugin.v(10250) | Removing sequential instance rx.lane1.fsm_state[0] because it is equivalent to instance rx.lane0.fsm_state[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : usb3_plugin.v(10250) | Removing user instance rx.lane1.fsm_state_1 because it is equivalent to instance rx.lane0.fsm_state_1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:FX493 :  | Applying initial value "000000000000" on instance ft601.cdc_fifo.fifo.unbuffered.consume_cdc_consume_r_gry[11:0]. 
@N:FX493 :  | Applying initial value "000000000000" on instance ft601.cdc_fifo.fifo.unbuffered.consume_w_bin[11:0]. 
@N:FX493 :  | Applying initial value "000000000000" on instance ft601.cdc_fifo.fifo.unbuffered.produce_cdc_produce_w_gry[11:0]. 
@N:FX493 :  | Applying initial value "000000000000" on instance ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage0[11:0]. 
@N:FX493 :  | Applying initial value "000000000000" on instance ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[11:0]. 
@N:FX493 :  | Applying initial value "000000000000" on instance ft601.cdc_fifo.fifo.unbuffered.consume_cdc.stage0[11:0]. 
@N:FX493 :  | Applying initial value "000000000000" on instance ft601.cdc_fifo.fifo.unbuffered.consume_cdc.stage1[11:0]. 
@N:FX493 :  | Applying initial value "00000000000000000000000000000000" on instance ft601.cdc_fifo.fifo.r_data[31:0]. 
@N:FX493 :  | Applying initial value "00000000000000000000000000000000" on instance jtag_controller.data[31:0]. 
@N:FX493 :  | Applying initial value "0000000" on instance jtag_controller.fsm_state[6:0]. 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)

@N:MO231 : usb3_plugin.v(11797) | Found counter in view:work.usb3_plugin(verilog) instance clocking.plugin_in.counter[31:0] 
@N:MF179 : usb3_plugin.v(14258) | Found 10 by 10 bit equality operator ('==') \$18 (in view: work.unbuffered(verilog))
@N:MF179 : usb3_plugin.v(14260) | Found 12 by 12 bit equality operator ('==') \$22 (in view: work.unbuffered(verilog))

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 153MB peak: 154MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 155MB peak: 164MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 156MB peak: 164MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 156MB peak: 164MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 164MB)


Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 164MB)


Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 192MB peak: 194MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:03s		    -4.69ns		 755 /       427
   2		0h:00m:03s		    -4.69ns		 745 /       427
   3		0h:00m:03s		    -4.37ns		 747 /       427
   4		0h:00m:03s		    -4.20ns		 748 /       427
   5		0h:00m:03s		    -4.37ns		 750 /       427
   6		0h:00m:03s		    -4.37ns		 751 /       427
   7		0h:00m:04s		    -4.37ns		 750 /       427
   8		0h:00m:04s		    -4.37ns		 751 /       427
@N:FX271 : usb3_plugin.v(6512) | Replicating instance jtag_controller.addr[7] (in view: work.usb3_plugin(verilog)) with 6 loads 1 time to improve timing.
@N:FX271 : usb3_plugin.v(6512) | Replicating instance jtag_controller.addr[2] (in view: work.usb3_plugin(verilog)) with 22 loads 1 time to improve timing.
@N:FX271 : usb3_plugin.v(6512) | Replicating instance jtag_controller.addr[3] (in view: work.usb3_plugin(verilog)) with 17 loads 1 time to improve timing.
Timing driven replication report
Added 3 Registers via timing driven replication
Added 1 LUTs via timing driven replication

   9		0h:00m:04s		    -4.60ns		 756 /       430
  10		0h:00m:04s		    -3.98ns		 763 /       430
  11		0h:00m:04s		    -3.94ns		 766 /       430
  12		0h:00m:05s		    -3.94ns		 768 /       430
  13		0h:00m:05s		    -3.94ns		 769 /       430
  14		0h:00m:05s		    -3.94ns		 770 /       430
  15		0h:00m:05s		    -3.94ns		 771 /       430
@N:FX271 : usb3_plugin.v(6512) | Replicating instance jtag_controller.addr[6] (in view: work.usb3_plugin(verilog)) with 11 loads 1 time to improve timing.
@N:FX271 : usb3_plugin.v(6512) | Replicating instance jtag_controller.addr[5] (in view: work.usb3_plugin(verilog)) with 15 loads 1 time to improve timing.
Added 2 Registers via timing driven replication
Added 1 LUTs via timing driven replication


  16		0h:00m:05s		    -3.92ns		 765 /       432
  17		0h:00m:05s		    -3.92ns		 769 /       432
  18		0h:00m:05s		    -3.92ns		 770 /       432
  19		0h:00m:05s		    -3.77ns		 773 /       432
  20		0h:00m:05s		    -3.77ns		 775 /       432
  21		0h:00m:05s		    -3.91ns		 775 /       432
  22		0h:00m:05s		    -3.66ns		 776 /       432
  23		0h:00m:05s		    -4.06ns		 777 /       432
  24		0h:00m:05s		    -4.06ns		 778 /       432
  25		0h:00m:05s		    -4.06ns		 777 /       432
  26		0h:00m:05s		    -4.06ns		 778 /       432

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 196MB peak: 197MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 197MB peak: 197MB)


Start Writing Netlists (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 160MB peak: 198MB)

Writing Analyst data base /home/anuejn/code/apertus/nGateware/src/experiments/build/usb3_plugin_Usb3Plugin_JTAG__19_Nov_2020__13_12_36/usb3_plugin_impl/synwork/usb3_plugin_impl_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 195MB peak: 198MB)

Writing EDIF Netlist and constraint files
@N:FX1056 :  | Writing EDF file: /home/anuejn/code/apertus/nGateware/src/experiments/build/usb3_plugin_Usb3Plugin_JTAG__19_Nov_2020__13_12_36/usb3_plugin_impl/usb3_plugin_impl.edi 
N-2018.03L-SP1-1
@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 200MB peak: 202MB)


Start final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 198MB peak: 202MB)

@W:MT246 : usb3_plugin.v(11723) | Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : usb3_plugin.v(351) | Blackbox ECLKSYNCA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : usb3_plugin.v(100) | Blackbox CLKDIVC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : usb3_plugin.v(789) | Blackbox JTAGF is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N:MT615 :  | Found clock plugin_stream_input_0__clk_word__p with period 20.00ns  
@N:MT615 :  | Found clock ft601_0__clk__io with period 10.00ns  
@N:MT615 :  | Found clock ft601_0__clk1__io with period 10.00ns  
@W:MT420 :  | Found inferred clock clk_div_quater|plugin_clk_inferred_clock with period 10.00ns. Please declare a user-defined clock on net rx.clk_div_quater.clocking_plugin_clk. 
@W:MT420 :  | Found inferred clock jtag|jtag_clk_inferred_clock with period 10.00ns. Please declare a user-defined clock on net jtag_controller.jtag.jtag_clk. 
@W:MT420 :  | Found inferred clock pll|plugin_ddr_clk_inferred_clock with period 10.00ns. Please declare a user-defined clock on net rx.pll.clocking_plugin_ddr_clk. 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Nov 19 13:14:20 2020
#


Top view:               usb3_plugin
Requested Frequency:    50.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    /home/anuejn/code/apertus/nGateware/src/experiments/build/usb3_plugin_Usb3Plugin_JTAG__19_Nov_2020__13_12_36/usb3_plugin.sdc
                       
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -5.199

                                             Requested     Estimated      Requested     Estimated                Clock        Clock              
Starting Clock                               Frequency     Frequency      Period        Period        Slack      Type         Group              
-------------------------------------------------------------------------------------------------------------------------------------------------
clk_div_quater|plugin_clk_inferred_clock     100.0 MHz     155.1 MHz      10.000        6.449         3.551      inferred     Inferred_clkgroup_0
ft601_0__clk1__io                            100.0 MHz     NA             10.000        NA            NA         declared     default_clkgroup   
ft601_0__clk__io                             100.0 MHz     88.8 MHz       10.000        11.259        -1.259     declared     default_clkgroup   
jtag|jtag_clk_inferred_clock                 100.0 MHz     65.8 MHz       10.000        15.198        -5.199     inferred     Inferred_clkgroup_1
pll|plugin_ddr_clk_inferred_clock            100.0 MHz     155.1 MHz      10.000        6.449         3.551      inferred     Inferred_clkgroup_2
plugin_stream_input_0__clk_word__p           50.0 MHz      156.6 MHz      20.000        6.385         13.615     declared     default_clkgroup   
System                                       100.0 MHz     1760.6 MHz     10.000        0.568         9.432      system       system_clkgroup    
=================================================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





Clock Relationships
*******************

Clocks                                                                              |    rise  to  rise    |    fall  to  fall    |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                  Ending                                    |  constraint  slack   |  constraint  slack   |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                    System                                    |  10.000      9.432   |  No paths    -       |  No paths    -      |  No paths    -    
System                                    clk_div_quater|plugin_clk_inferred_clock  |  10.000      8.629   |  No paths    -       |  No paths    -      |  No paths    -    
System                                    jtag|jtag_clk_inferred_clock              |  No paths    -       |  No paths    -       |  10.000      5.229  |  No paths    -    
System                                    pll|plugin_ddr_clk_inferred_clock         |  10.000      8.629   |  No paths    -       |  No paths    -      |  No paths    -    
plugin_stream_input_0__clk_word__p        plugin_stream_input_0__clk_word__p        |  20.000      13.615  |  No paths    -       |  No paths    -      |  No paths    -    
plugin_stream_input_0__clk_word__p        jtag|jtag_clk_inferred_clock              |  No paths    -       |  No paths    -       |  Diff grp    -      |  No paths    -    
ft601_0__clk__io                          ft601_0__clk__io                          |  10.000      -1.259  |  No paths    -       |  No paths    -      |  No paths    -    
ft601_0__clk__io                          jtag|jtag_clk_inferred_clock              |  No paths    -       |  No paths    -       |  Diff grp    -      |  No paths    -    
clk_div_quater|plugin_clk_inferred_clock  clk_div_quater|plugin_clk_inferred_clock  |  10.000      3.551   |  No paths    -       |  No paths    -      |  No paths    -    
clk_div_quater|plugin_clk_inferred_clock  jtag|jtag_clk_inferred_clock              |  No paths    -       |  No paths    -       |  Diff grp    -      |  No paths    -    
jtag|jtag_clk_inferred_clock              System                                    |  No paths    -       |  No paths    -       |  No paths    -      |  10.000      3.295
jtag|jtag_clk_inferred_clock              ft601_0__clk__io                          |  No paths    -       |  No paths    -       |  No paths    -      |  Diff grp    -    
jtag|jtag_clk_inferred_clock              jtag|jtag_clk_inferred_clock              |  No paths    -       |  10.000      -5.199  |  No paths    -      |  No paths    -    
pll|plugin_ddr_clk_inferred_clock         jtag|jtag_clk_inferred_clock              |  No paths    -       |  No paths    -       |  Diff grp    -      |  No paths    -    
pll|plugin_ddr_clk_inferred_clock         pll|plugin_ddr_clk_inferred_clock         |  10.000      3.551   |  No paths    -       |  No paths    -      |  No paths    -    
============================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: clk_div_quater|plugin_clk_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                               Starting                                                                                 Arrival          
Instance                       Reference                                    Type        Pin     Net                     Time        Slack
                               Clock                                                                                                     
-----------------------------------------------------------------------------------------------------------------------------------------
clocking.plugin.counter[0]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     Q       clocking_counter[0]     1.108       3.551
clocking.plugin.counter[1]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     Q       clocking_counter[1]     1.044       3.758
clocking.plugin.counter[2]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     Q       clocking_counter[2]     1.044       3.758
clocking.plugin.counter[3]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     Q       clocking_counter[3]     1.044       3.901
clocking.plugin.counter[4]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     Q       clocking_counter[4]     1.044       3.901
clocking.plugin.counter[5]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     Q       clocking_counter[5]     1.044       4.043
clocking.plugin.counter[6]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     Q       clocking_counter[6]     1.044       4.043
clocking.plugin.counter[7]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     Q       clocking_counter[7]     1.044       4.186
clocking.plugin.counter[8]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     Q       clocking_counter[8]     1.044       4.186
clocking.plugin.counter[9]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     Q       clocking_counter[9]     1.044       4.329
=========================================================================================================================================


Ending Points with Worst Slack
******************************

                                Starting                                                                      Required          
Instance                        Reference                                    Type        Pin     Net          Time         Slack
                                Clock                                                                                           
--------------------------------------------------------------------------------------------------------------------------------
clocking.plugin.counter[31]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     D       Z\$2[31]     9.894        3.551
clocking.plugin.counter[29]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     D       Z\$2[29]     9.894        3.694
clocking.plugin.counter[30]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     D       Z\$2[30]     9.894        3.694
clocking.plugin.counter[27]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     D       Z\$2[27]     9.894        3.837
clocking.plugin.counter[28]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     D       Z\$2[28]     9.894        3.837
clocking.plugin.counter[25]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     D       Z\$2[25]     9.894        3.979
clocking.plugin.counter[26]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     D       Z\$2[26]     9.894        3.979
clocking.plugin.counter[23]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     D       Z\$2[23]     9.894        4.122
clocking.plugin.counter[24]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     D       Z\$2[24]     9.894        4.122
clocking.plugin.counter[21]     clk_div_quater|plugin_clk_inferred_clock     FD1S3IX     D       Z\$2[21]     9.894        4.265
================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.894

    - Propagation time:                      6.343
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 3.551

    Number of logic level(s):                17
    Starting point:                          clocking.plugin.counter[0] / Q
    Ending point:                            clocking.plugin.counter[31] / D
    The start point is clocked by            clk_div_quater|plugin_clk_inferred_clock [rising] on pin CK
    The end   point is clocked by            clk_div_quater|plugin_clk_inferred_clock [rising] on pin CK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                             Type        Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
clocking.plugin.counter[0]       FD1S3IX     Q        Out     1.108     1.108       -         
clocking_counter[0]              Net         -        -       -         -           3         
clocking.plugin.\$2_cry_0_0      CCU2D       A1       In      0.000     1.108       -         
clocking.plugin.\$2_cry_0_0      CCU2D       COUT     Out     1.544     2.652       -         
Z\$2_cry_0                       Net         -        -       -         -           1         
clocking.plugin.\$2_cry_1_0      CCU2D       CIN      In      0.000     2.652       -         
clocking.plugin.\$2_cry_1_0      CCU2D       COUT     Out     0.143     2.795       -         
Z\$2_cry_2                       Net         -        -       -         -           1         
clocking.plugin.\$2_cry_3_0      CCU2D       CIN      In      0.000     2.795       -         
clocking.plugin.\$2_cry_3_0      CCU2D       COUT     Out     0.143     2.938       -         
Z\$2_cry_4                       Net         -        -       -         -           1         
clocking.plugin.\$2_cry_5_0      CCU2D       CIN      In      0.000     2.938       -         
clocking.plugin.\$2_cry_5_0      CCU2D       COUT     Out     0.143     3.081       -         
Z\$2_cry_6                       Net         -        -       -         -           1         
clocking.plugin.\$2_cry_7_0      CCU2D       CIN      In      0.000     3.081       -         
clocking.plugin.\$2_cry_7_0      CCU2D       COUT     Out     0.143     3.224       -         
Z\$2_cry_8                       Net         -        -       -         -           1         
clocking.plugin.\$2_cry_9_0      CCU2D       CIN      In      0.000     3.224       -         
clocking.plugin.\$2_cry_9_0      CCU2D       COUT     Out     0.143     3.366       -         
Z\$2_cry_10                      Net         -        -       -         -           1         
clocking.plugin.\$2_cry_11_0     CCU2D       CIN      In      0.000     3.366       -         
clocking.plugin.\$2_cry_11_0     CCU2D       COUT     Out     0.143     3.509       -         
Z\$2_cry_12                      Net         -        -       -         -           1         
clocking.plugin.\$2_cry_13_0     CCU2D       CIN      In      0.000     3.509       -         
clocking.plugin.\$2_cry_13_0     CCU2D       COUT     Out     0.143     3.652       -         
Z\$2_cry_14                      Net         -        -       -         -           1         
clocking.plugin.\$2_cry_15_0     CCU2D       CIN      In      0.000     3.652       -         
clocking.plugin.\$2_cry_15_0     CCU2D       COUT     Out     0.143     3.795       -         
Z\$2_cry_16                      Net         -        -       -         -           1         
clocking.plugin.\$2_cry_17_0     CCU2D       CIN      In      0.000     3.795       -         
clocking.plugin.\$2_cry_17_0     CCU2D       COUT     Out     0.143     3.938       -         
Z\$2_cry_18                      Net         -        -       -         -           1         
clocking.plugin.\$2_cry_19_0     CCU2D       CIN      In      0.000     3.938       -         
clocking.plugin.\$2_cry_19_0     CCU2D       COUT     Out     0.143     4.080       -         
Z\$2_cry_20                      Net         -        -       -         -           1         
clocking.plugin.\$2_cry_21_0     CCU2D       CIN      In      0.000     4.080       -         
clocking.plugin.\$2_cry_21_0     CCU2D       COUT     Out     0.143     4.223       -         
Z\$2_cry_22                      Net         -        -       -         -           1         
clocking.plugin.\$2_cry_23_0     CCU2D       CIN      In      0.000     4.223       -         
clocking.plugin.\$2_cry_23_0     CCU2D       COUT     Out     0.143     4.366       -         
Z\$2_cry_24                      Net         -        -       -         -           1         
clocking.plugin.\$2_cry_25_0     CCU2D       CIN      In      0.000     4.366       -         
clocking.plugin.\$2_cry_25_0     CCU2D       COUT     Out     0.143     4.509       -         
Z\$2_cry_26                      Net         -        -       -         -           1         
clocking.plugin.\$2_cry_27_0     CCU2D       CIN      In      0.000     4.509       -         
clocking.plugin.\$2_cry_27_0     CCU2D       COUT     Out     0.143     4.652       -         
Z\$2_cry_28                      Net         -        -       -         -           1         
clocking.plugin.\$2_cry_29_0     CCU2D       CIN      In      0.000     4.652       -         
clocking.plugin.\$2_cry_29_0     CCU2D       COUT     Out     0.143     4.794       -         
Z\$2_cry_30                      Net         -        -       -         -           1         
clocking.plugin.\$2_s_31_0       CCU2D       CIN      In      0.000     4.794       -         
clocking.plugin.\$2_s_31_0       CCU2D       S0       Out     1.549     6.343       -         
Z\$2[31]                         Net         -        -       -         -           1         
clocking.plugin.counter[31]      FD1S3IX     D        In      0.000     6.343       -         
==============================================================================================




====================================
Detailed Report for Clock: ft601_0__clk__io
====================================



Starting Points with Worst Slack
********************************

                                                                Starting                                                                  Arrival           
Instance                                                        Reference            Type        Pin     Net                              Time        Slack 
                                                                Clock                                                                                       
------------------------------------------------------------------------------------------------------------------------------------------------------------
ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[1]            ft601_0__clk__io     FD1S3AX     Q       produce_cdc_produce_r_gry[1]     1.180       -1.259
ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[0]            ft601_0__clk__io     FD1S3AX     Q       produce_cdc_produce_r_gry[0]     1.108       -1.187
ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[3]            ft601_0__clk__io     FD1S3AX     Q       produce_cdc_produce_r_gry[3]     1.188       -1.124
ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[5]            ft601_0__clk__io     FD1S3AX     Q       produce_cdc_produce_r_gry[5]     1.188       -1.124
ft601.cdc_fifo.fifo.unbuffered.consume_cdc_consume_r_gry[0]     ft601_0__clk__io     FD1S3AX     Q       consume_cdc_consume_r_gry[0]     1.044       -1.123
ft601.cdc_fifo.fifo.unbuffered.consume_cdc_consume_r_gry[1]     ft601_0__clk__io     FD1S3AX     Q       consume_cdc_consume_r_gry[1]     1.044       -1.123
ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[2]            ft601_0__clk__io     FD1S3AX     Q       produce_cdc_produce_r_gry[2]     1.180       -1.116
ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[4]            ft601_0__clk__io     FD1S3AX     Q       produce_cdc_produce_r_gry[4]     1.148       -1.084
ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[8]            ft601_0__clk__io     FD1S3AX     Q       produce_cdc_produce_r_gry[8]     1.204       -0.997
ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[9]            ft601_0__clk__io     FD1S3AX     Q       produce_cdc_produce_r_gry[9]     1.188       -0.981
============================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                       Starting                                               Required           
Instance                                               Reference            Type      Pin       Net           Time         Slack 
                                                       Clock                                                                     
---------------------------------------------------------------------------------------------------------------------------------
ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_0     ft601_0__clk__io     DP8KC     ADA11     Z\$10[9]      8.318        -1.259
ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_0     ft601_0__clk__io     DP8KC     ADA12     Z\$10[10]     8.318        -1.259
ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_1     ft601_0__clk__io     DP8KC     ADA11     Z\$10[9]      8.318        -1.259
ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_1     ft601_0__clk__io     DP8KC     ADA12     Z\$10[10]     8.318        -1.259
ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_2     ft601_0__clk__io     DP8KC     ADA11     Z\$10[9]      8.318        -1.259
ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_2     ft601_0__clk__io     DP8KC     ADA12     Z\$10[10]     8.318        -1.259
ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_3     ft601_0__clk__io     DP8KC     ADA11     Z\$10[9]      8.318        -1.259
ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_3     ft601_0__clk__io     DP8KC     ADA12     Z\$10[10]     8.318        -1.259
ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_4     ft601_0__clk__io     DP8KC     ADA11     Z\$10[9]      8.318        -1.259
ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_4     ft601_0__clk__io     DP8KC     ADA12     Z\$10[10]     8.318        -1.259
=================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            1.682
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.318

    - Propagation time:                      9.576
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.259

    Number of logic level(s):                11
    Starting point:                          ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[1] / Q
    Ending point:                            ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_0 / ADA12
    The start point is clocked by            ft601_0__clk__io [rising] on pin CK
    The end   point is clocked by            ft601_0__clk__io [rising] on pin CLKA

Instance / Net                                                        Pin       Pin               Arrival     No. of    
Name                                                     Type         Name      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------
ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[1]     FD1S3AX      Q         Out     1.180     1.180       -         
produce_cdc_produce_r_gry[1]                             Net          -         -       -         -           5         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_1_0              CCU2D        D1        In      0.000     1.180       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_1_0              CCU2D        COUT      Out     1.544     2.724       -         
Z\$22_0_data_tmp[0]                                      Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_15_0             CCU2D        CIN       In      0.000     2.724       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_15_0             CCU2D        COUT      Out     0.143     2.867       -         
Z\$22_0_data_tmp[2]                                      Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_21_0             CCU2D        CIN       In      0.000     2.867       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_21_0             CCU2D        COUT      Out     0.143     3.010       -         
Z\$22_0_data_tmp[4]                                      Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_9_0              CCU2D        CIN       In      0.000     3.010       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_9_0              CCU2D        S1        Out     1.621     4.631       -         
Z\$22_0_data_tmp_i[5]                                    Net          -         -       -         -           2         
ft601.cdc_fifo.fifo.unbuffered.\$8                       ORCALUT4     B         In      0.000     4.631       -         
ft601.cdc_fifo.fifo.unbuffered.\$8                       ORCALUT4     Z         Out     1.017     5.648       -         
Z\$8                                                     Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_0_0              CCU2D        B0        In      0.000     5.648       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_0_0              CCU2D        COUT      Out     1.544     7.192       -         
Z\$10_cry_0                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_1_0              CCU2D        CIN       In      0.000     7.192       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_1_0              CCU2D        COUT      Out     0.143     7.335       -         
Z\$10_cry_2                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_3_0              CCU2D        CIN       In      0.000     7.335       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_3_0              CCU2D        COUT      Out     0.143     7.478       -         
Z\$10_cry_4                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_5_0              CCU2D        CIN       In      0.000     7.478       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_5_0              CCU2D        COUT      Out     0.143     7.621       -         
Z\$10_cry_6                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_7_0              CCU2D        CIN       In      0.000     7.621       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_7_0              CCU2D        COUT      Out     0.143     7.763       -         
Z\$10_cry_8                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_9_0              CCU2D        CIN       In      0.000     7.763       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_9_0              CCU2D        S1        Out     1.813     9.576       -         
Z\$10[10]                                                Net          -         -       -         -           11        
ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_0       DP8KC        ADA12     In      0.000     9.576       -         
========================================================================================================================


Path information for path number 2: 
      Requested Period:                      10.000
    - Setup time:                            1.682
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.318

    - Propagation time:                      9.576
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.259

    Number of logic level(s):                11
    Starting point:                          ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[1] / Q
    Ending point:                            ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_0 / ADA11
    The start point is clocked by            ft601_0__clk__io [rising] on pin CK
    The end   point is clocked by            ft601_0__clk__io [rising] on pin CLKA

Instance / Net                                                        Pin       Pin               Arrival     No. of    
Name                                                     Type         Name      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------
ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[1]     FD1S3AX      Q         Out     1.180     1.180       -         
produce_cdc_produce_r_gry[1]                             Net          -         -       -         -           5         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_1_0              CCU2D        D1        In      0.000     1.180       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_1_0              CCU2D        COUT      Out     1.544     2.724       -         
Z\$22_0_data_tmp[0]                                      Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_15_0             CCU2D        CIN       In      0.000     2.724       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_15_0             CCU2D        COUT      Out     0.143     2.867       -         
Z\$22_0_data_tmp[2]                                      Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_21_0             CCU2D        CIN       In      0.000     2.867       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_21_0             CCU2D        COUT      Out     0.143     3.010       -         
Z\$22_0_data_tmp[4]                                      Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_9_0              CCU2D        CIN       In      0.000     3.010       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_9_0              CCU2D        S1        Out     1.621     4.631       -         
Z\$22_0_data_tmp_i[5]                                    Net          -         -       -         -           2         
ft601.cdc_fifo.fifo.unbuffered.\$8                       ORCALUT4     B         In      0.000     4.631       -         
ft601.cdc_fifo.fifo.unbuffered.\$8                       ORCALUT4     Z         Out     1.017     5.648       -         
Z\$8                                                     Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_0_0              CCU2D        B0        In      0.000     5.648       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_0_0              CCU2D        COUT      Out     1.544     7.192       -         
Z\$10_cry_0                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_1_0              CCU2D        CIN       In      0.000     7.192       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_1_0              CCU2D        COUT      Out     0.143     7.335       -         
Z\$10_cry_2                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_3_0              CCU2D        CIN       In      0.000     7.335       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_3_0              CCU2D        COUT      Out     0.143     7.478       -         
Z\$10_cry_4                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_5_0              CCU2D        CIN       In      0.000     7.478       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_5_0              CCU2D        COUT      Out     0.143     7.621       -         
Z\$10_cry_6                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_7_0              CCU2D        CIN       In      0.000     7.621       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_7_0              CCU2D        COUT      Out     0.143     7.763       -         
Z\$10_cry_8                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_9_0              CCU2D        CIN       In      0.000     7.763       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_9_0              CCU2D        S0        Out     1.813     9.576       -         
Z\$10[9]                                                 Net          -         -       -         -           11        
ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_0       DP8KC        ADA11     In      0.000     9.576       -         
========================================================================================================================


Path information for path number 3: 
      Requested Period:                      10.000
    - Setup time:                            1.682
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.318

    - Propagation time:                      9.576
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.259

    Number of logic level(s):                11
    Starting point:                          ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[1] / Q
    Ending point:                            ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_7 / ADA12
    The start point is clocked by            ft601_0__clk__io [rising] on pin CK
    The end   point is clocked by            ft601_0__clk__io [rising] on pin CLKA

Instance / Net                                                        Pin       Pin               Arrival     No. of    
Name                                                     Type         Name      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------
ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[1]     FD1S3AX      Q         Out     1.180     1.180       -         
produce_cdc_produce_r_gry[1]                             Net          -         -       -         -           5         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_1_0              CCU2D        D1        In      0.000     1.180       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_1_0              CCU2D        COUT      Out     1.544     2.724       -         
Z\$22_0_data_tmp[0]                                      Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_15_0             CCU2D        CIN       In      0.000     2.724       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_15_0             CCU2D        COUT      Out     0.143     2.867       -         
Z\$22_0_data_tmp[2]                                      Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_21_0             CCU2D        CIN       In      0.000     2.867       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_21_0             CCU2D        COUT      Out     0.143     3.010       -         
Z\$22_0_data_tmp[4]                                      Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_9_0              CCU2D        CIN       In      0.000     3.010       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_9_0              CCU2D        S1        Out     1.621     4.631       -         
Z\$22_0_data_tmp_i[5]                                    Net          -         -       -         -           2         
ft601.cdc_fifo.fifo.unbuffered.\$8                       ORCALUT4     B         In      0.000     4.631       -         
ft601.cdc_fifo.fifo.unbuffered.\$8                       ORCALUT4     Z         Out     1.017     5.648       -         
Z\$8                                                     Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_0_0              CCU2D        B0        In      0.000     5.648       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_0_0              CCU2D        COUT      Out     1.544     7.192       -         
Z\$10_cry_0                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_1_0              CCU2D        CIN       In      0.000     7.192       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_1_0              CCU2D        COUT      Out     0.143     7.335       -         
Z\$10_cry_2                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_3_0              CCU2D        CIN       In      0.000     7.335       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_3_0              CCU2D        COUT      Out     0.143     7.478       -         
Z\$10_cry_4                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_5_0              CCU2D        CIN       In      0.000     7.478       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_5_0              CCU2D        COUT      Out     0.143     7.621       -         
Z\$10_cry_6                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_7_0              CCU2D        CIN       In      0.000     7.621       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_7_0              CCU2D        COUT      Out     0.143     7.763       -         
Z\$10_cry_8                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_9_0              CCU2D        CIN       In      0.000     7.763       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_9_0              CCU2D        S1        Out     1.813     9.576       -         
Z\$10[10]                                                Net          -         -       -         -           11        
ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_7       DP8KC        ADA12     In      0.000     9.576       -         
========================================================================================================================


Path information for path number 4: 
      Requested Period:                      10.000
    - Setup time:                            1.682
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.318

    - Propagation time:                      9.576
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.259

    Number of logic level(s):                11
    Starting point:                          ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[1] / Q
    Ending point:                            ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_6 / ADA12
    The start point is clocked by            ft601_0__clk__io [rising] on pin CK
    The end   point is clocked by            ft601_0__clk__io [rising] on pin CLKA

Instance / Net                                                        Pin       Pin               Arrival     No. of    
Name                                                     Type         Name      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------
ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[1]     FD1S3AX      Q         Out     1.180     1.180       -         
produce_cdc_produce_r_gry[1]                             Net          -         -       -         -           5         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_1_0              CCU2D        D1        In      0.000     1.180       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_1_0              CCU2D        COUT      Out     1.544     2.724       -         
Z\$22_0_data_tmp[0]                                      Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_15_0             CCU2D        CIN       In      0.000     2.724       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_15_0             CCU2D        COUT      Out     0.143     2.867       -         
Z\$22_0_data_tmp[2]                                      Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_21_0             CCU2D        CIN       In      0.000     2.867       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_21_0             CCU2D        COUT      Out     0.143     3.010       -         
Z\$22_0_data_tmp[4]                                      Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_9_0              CCU2D        CIN       In      0.000     3.010       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_9_0              CCU2D        S1        Out     1.621     4.631       -         
Z\$22_0_data_tmp_i[5]                                    Net          -         -       -         -           2         
ft601.cdc_fifo.fifo.unbuffered.\$8                       ORCALUT4     B         In      0.000     4.631       -         
ft601.cdc_fifo.fifo.unbuffered.\$8                       ORCALUT4     Z         Out     1.017     5.648       -         
Z\$8                                                     Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_0_0              CCU2D        B0        In      0.000     5.648       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_0_0              CCU2D        COUT      Out     1.544     7.192       -         
Z\$10_cry_0                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_1_0              CCU2D        CIN       In      0.000     7.192       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_1_0              CCU2D        COUT      Out     0.143     7.335       -         
Z\$10_cry_2                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_3_0              CCU2D        CIN       In      0.000     7.335       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_3_0              CCU2D        COUT      Out     0.143     7.478       -         
Z\$10_cry_4                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_5_0              CCU2D        CIN       In      0.000     7.478       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_5_0              CCU2D        COUT      Out     0.143     7.621       -         
Z\$10_cry_6                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_7_0              CCU2D        CIN       In      0.000     7.621       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_7_0              CCU2D        COUT      Out     0.143     7.763       -         
Z\$10_cry_8                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_9_0              CCU2D        CIN       In      0.000     7.763       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_9_0              CCU2D        S1        Out     1.813     9.576       -         
Z\$10[10]                                                Net          -         -       -         -           11        
ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_6       DP8KC        ADA12     In      0.000     9.576       -         
========================================================================================================================


Path information for path number 5: 
      Requested Period:                      10.000
    - Setup time:                            1.682
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.318

    - Propagation time:                      9.576
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.259

    Number of logic level(s):                11
    Starting point:                          ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[1] / Q
    Ending point:                            ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_5 / ADA12
    The start point is clocked by            ft601_0__clk__io [rising] on pin CK
    The end   point is clocked by            ft601_0__clk__io [rising] on pin CLKA

Instance / Net                                                        Pin       Pin               Arrival     No. of    
Name                                                     Type         Name      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------
ft601.cdc_fifo.fifo.unbuffered.produce_cdc.stage1[1]     FD1S3AX      Q         Out     1.180     1.180       -         
produce_cdc_produce_r_gry[1]                             Net          -         -       -         -           5         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_1_0              CCU2D        D1        In      0.000     1.180       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_1_0              CCU2D        COUT      Out     1.544     2.724       -         
Z\$22_0_data_tmp[0]                                      Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_15_0             CCU2D        CIN       In      0.000     2.724       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_15_0             CCU2D        COUT      Out     0.143     2.867       -         
Z\$22_0_data_tmp[2]                                      Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_21_0             CCU2D        CIN       In      0.000     2.867       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_21_0             CCU2D        COUT      Out     0.143     3.010       -         
Z\$22_0_data_tmp[4]                                      Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_9_0              CCU2D        CIN       In      0.000     3.010       -         
ft601.cdc_fifo.fifo.unbuffered.\$22_0_I_9_0              CCU2D        S1        Out     1.621     4.631       -         
Z\$22_0_data_tmp_i[5]                                    Net          -         -       -         -           2         
ft601.cdc_fifo.fifo.unbuffered.\$8                       ORCALUT4     B         In      0.000     4.631       -         
ft601.cdc_fifo.fifo.unbuffered.\$8                       ORCALUT4     Z         Out     1.017     5.648       -         
Z\$8                                                     Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_0_0              CCU2D        B0        In      0.000     5.648       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_0_0              CCU2D        COUT      Out     1.544     7.192       -         
Z\$10_cry_0                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_1_0              CCU2D        CIN       In      0.000     7.192       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_1_0              CCU2D        COUT      Out     0.143     7.335       -         
Z\$10_cry_2                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_3_0              CCU2D        CIN       In      0.000     7.335       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_3_0              CCU2D        COUT      Out     0.143     7.478       -         
Z\$10_cry_4                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_5_0              CCU2D        CIN       In      0.000     7.478       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_5_0              CCU2D        COUT      Out     0.143     7.621       -         
Z\$10_cry_6                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_7_0              CCU2D        CIN       In      0.000     7.621       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_7_0              CCU2D        COUT      Out     0.143     7.763       -         
Z\$10_cry_8                                              Net          -         -       -         -           1         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_9_0              CCU2D        CIN       In      0.000     7.763       -         
ft601.cdc_fifo.fifo.unbuffered.\$10_cry_9_0              CCU2D        S1        Out     1.813     9.576       -         
Z\$10[10]                                                Net          -         -       -         -           11        
ft601.cdc_fifo.fifo.unbuffered.storage_storage_0_5       DP8KC        ADA12     In      0.000     9.576       -         
========================================================================================================================




====================================
Detailed Report for Clock: jtag|jtag_clk_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                 Starting                                                              Arrival           
Instance                         Reference                        Type        Pin     Net              Time        Slack 
                                 Clock                                                                                   
-------------------------------------------------------------------------------------------------------------------------
jtag_controller.addr_fast[2]     jtag|jtag_clk_inferred_clock     FD1P3AX     Q       addr_fast[2]     0.972       -5.199
jtag_controller.addr_fast[3]     jtag|jtag_clk_inferred_clock     FD1P3AX     Q       addr_fast[3]     1.044       -5.168
jtag_controller.addr_fast[7]     jtag|jtag_clk_inferred_clock     FD1P3AX     Q       addr_fast[7]     1.044       -5.141
jtag_controller.addr_fast[6]     jtag|jtag_clk_inferred_clock     FD1P3AX     Q       addr_fast[6]     1.044       -5.065
jtag_controller.addr_fast[5]     jtag|jtag_clk_inferred_clock     FD1P3AX     Q       addr_fast[5]     1.044       -4.979
jtag_controller.addr[4]          jtag|jtag_clk_inferred_clock     FD1P3AX     Q       addr[4]          1.272       -4.965
jtag_controller.addr[3]          jtag|jtag_clk_inferred_clock     FD1P3AX     Q       addr[3]          1.260       -4.173
jtag_controller.addr[5]          jtag|jtag_clk_inferred_clock     FD1P3AX     Q       addr[5]          1.256       -4.026
jtag_controller.addr[6]          jtag|jtag_clk_inferred_clock     FD1P3AX     Q       addr[6]          1.232       -4.002
jtag_controller.addr[8]          jtag|jtag_clk_inferred_clock     FD1P3AX     Q       addr[8]          1.236       -3.863
=========================================================================================================================


Ending Points with Worst Slack
******************************

                            Starting                                                                     Required           
Instance                    Reference                        Type        Pin     Net                     Time         Slack 
                            Clock                                                                                           
----------------------------------------------------------------------------------------------------------------------------
jtag_controller.data[0]     jtag|jtag_clk_inferred_clock     FD1P3AX     SP      un1_data\$next284_i     9.528        -5.199
jtag_controller.data[1]     jtag|jtag_clk_inferred_clock     FD1P3AX     SP      un1_data\$next284_i     9.528        -5.199
jtag_controller.data[2]     jtag|jtag_clk_inferred_clock     FD1P3AX     SP      un1_data\$next284_i     9.528        -5.199
jtag_controller.data[3]     jtag|jtag_clk_inferred_clock     FD1P3AX     SP      un1_data\$next284_i     9.528        -5.199
jtag_controller.data[4]     jtag|jtag_clk_inferred_clock     FD1P3AX     SP      un1_data\$next284_i     9.528        -5.199
jtag_controller.data[5]     jtag|jtag_clk_inferred_clock     FD1P3AX     SP      un1_data\$next284_i     9.528        -5.199
jtag_controller.data[6]     jtag|jtag_clk_inferred_clock     FD1P3AX     SP      un1_data\$next284_i     9.528        -5.199
jtag_controller.data[7]     jtag|jtag_clk_inferred_clock     FD1P3AX     SP      un1_data\$next284_i     9.528        -5.199
jtag_controller.data[8]     jtag|jtag_clk_inferred_clock     FD1P3AX     SP      un1_data\$next284_i     9.528        -5.199
jtag_controller.data[9]     jtag|jtag_clk_inferred_clock     FD1P3AX     SP      un1_data\$next284_i     9.528        -5.199
============================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.528

    - Propagation time:                      14.727
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -5.199

    Number of logic level(s):                21
    Starting point:                          jtag_controller.addr_fast[2] / Q
    Ending point:                            jtag_controller.data[0] / SP
    The start point is clocked by            jtag|jtag_clk_inferred_clock [falling] on pin CK
    The end   point is clocked by            jtag|jtag_clk_inferred_clock [falling] on pin CK

Instance / Net                                                        Pin      Pin               Arrival     No. of    
Name                                                     Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------
jtag_controller.addr_fast[2]                             FD1P3AX      Q        Out     0.972     0.972       -         
addr_fast[2]                                             Net          -        -       -         -           1         
jtag_controller.\$1245_cry_0_0                           CCU2D        A1       In      0.000     0.972       -         
jtag_controller.\$1245_cry_0_0                           CCU2D        S1       Out     1.346     2.318       -         
addr_i[2]                                                Net          -        -       -         -           3         
jtag_controller.\$1074_1_cry_0_0                         CCU2D        A1       In      0.000     2.318       -         
jtag_controller.\$1074_1_cry_0_0                         CCU2D        COUT     Out     1.544     3.862       -         
Z\$1074_1_cry_0                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_1_0                         CCU2D        CIN      In      0.000     3.862       -         
jtag_controller.\$1074_1_cry_1_0                         CCU2D        COUT     Out     0.143     4.005       -         
Z\$1074_1_cry_2                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_3_0                         CCU2D        CIN      In      0.000     4.005       -         
jtag_controller.\$1074_1_cry_3_0                         CCU2D        COUT     Out     0.143     4.148       -         
Z\$1074_1_cry_4                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_5_0                         CCU2D        CIN      In      0.000     4.148       -         
jtag_controller.\$1074_1_cry_5_0                         CCU2D        COUT     Out     0.143     4.291       -         
Z\$1074_1_cry_6                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_7_0                         CCU2D        CIN      In      0.000     4.291       -         
jtag_controller.\$1074_1_cry_7_0                         CCU2D        COUT     Out     0.143     4.434       -         
Z\$1074_1_cry_8                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_9_0                         CCU2D        CIN      In      0.000     4.434       -         
jtag_controller.\$1074_1_cry_9_0                         CCU2D        COUT     Out     0.143     4.576       -         
Z\$1074_1_cry_10                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_11_0                        CCU2D        CIN      In      0.000     4.576       -         
jtag_controller.\$1074_1_cry_11_0                        CCU2D        COUT     Out     0.143     4.719       -         
Z\$1074_1_cry_12                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_13_0                        CCU2D        CIN      In      0.000     4.719       -         
jtag_controller.\$1074_1_cry_13_0                        CCU2D        COUT     Out     0.143     4.862       -         
Z\$1074_1_cry_14                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_15_0                        CCU2D        CIN      In      0.000     4.862       -         
jtag_controller.\$1074_1_cry_15_0                        CCU2D        COUT     Out     0.143     5.005       -         
Z\$1074_1_cry_16                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_17_0                        CCU2D        CIN      In      0.000     5.005       -         
jtag_controller.\$1074_1_cry_17_0                        CCU2D        COUT     Out     0.143     5.147       -         
Z\$1074_1_cry_18                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_19_0                        CCU2D        CIN      In      0.000     5.147       -         
jtag_controller.\$1074_1_cry_19_0                        CCU2D        COUT     Out     0.143     5.290       -         
Z\$1074_1_cry_20                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_21_0                        CCU2D        CIN      In      0.000     5.290       -         
jtag_controller.\$1074_1_cry_21_0                        CCU2D        COUT     Out     0.143     5.433       -         
Z\$1074_1_cry_22                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_23_0                        CCU2D        CIN      In      0.000     5.433       -         
jtag_controller.\$1074_1_cry_23_0                        CCU2D        S1       Out     1.549     6.982       -         
Z\$1074_1[26]                                            Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_15_0_RNI1J8E                ORCALUT4     D        In      0.000     6.982       -         
jtag_controller.\$1074_1_cry_15_0_RNI1J8E                ORCALUT4     Z        Out     1.017     7.999       -         
data\$next_104_sn_m27_639_i_a2_0_16                      Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_11_0_RNIU7MI1               ORCALUT4     D        In      0.000     7.999       -         
jtag_controller.\$1074_1_cry_11_0_RNIU7MI1               ORCALUT4     Z        Out     1.017     9.016       -         
data\$next_104_sn_m27_639_i_a2_0_25                      Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_27_0_RNIK3JB3               ORCALUT4     D        In      0.000     9.016       -         
jtag_controller.\$1074_1_cry_27_0_RNIK3JB3               ORCALUT4     Z        Out     1.153     10.168      -         
N_123                                                    Net          -        -       -         -           3         
jtag_controller.data\$next_2_sqmuxa_4                    ORCALUT4     D        In      0.000     10.168      -         
jtag_controller.data\$next_2_sqmuxa_4                    ORCALUT4     Z        Out     1.017     11.185      -         
data\$next_2_sqmuxa_4                                    Net          -        -       -         -           1         
jtag_controller.un1_data\$next_2_sqmuxa_9_0              ORCALUT4     A        In      0.000     11.185      -         
jtag_controller.un1_data\$next_2_sqmuxa_9_0              ORCALUT4     Z        Out     1.089     12.274      -         
un1_data\$next_2_sqmuxa_9_0                              Net          -        -       -         -           2         
jtag_controller.un1_data\$next_2_sqmuxa_9_0_RNIP8LUA     ORCALUT4     D        In      0.000     12.274      -         
jtag_controller.un1_data\$next_2_sqmuxa_9_0_RNIP8LUA     ORCALUT4     Z        Out     1.089     13.363      -         
un1_data\$next_2_sqmuxa_9                                Net          -        -       -         -           2         
jtag_controller.un1_data\$next_2_sqmuxa_8_5_RNI349VF     ORCALUT4     D        In      0.000     13.363      -         
jtag_controller.un1_data\$next_2_sqmuxa_8_5_RNI349VF     ORCALUT4     Z        Out     1.364     14.727      -         
un1_data\$next284_i                                      Net          -        -       -         -           32        
jtag_controller.data[0]                                  FD1P3AX      SP       In      0.000     14.727      -         
=======================================================================================================================


Path information for path number 2: 
      Requested Period:                      10.000
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.528

    - Propagation time:                      14.727
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -5.199

    Number of logic level(s):                21
    Starting point:                          jtag_controller.addr_fast[2] / Q
    Ending point:                            jtag_controller.data[0] / SP
    The start point is clocked by            jtag|jtag_clk_inferred_clock [falling] on pin CK
    The end   point is clocked by            jtag|jtag_clk_inferred_clock [falling] on pin CK

Instance / Net                                                        Pin      Pin               Arrival     No. of    
Name                                                     Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------
jtag_controller.addr_fast[2]                             FD1P3AX      Q        Out     0.972     0.972       -         
addr_fast[2]                                             Net          -        -       -         -           1         
jtag_controller.\$1245_cry_0_0                           CCU2D        A1       In      0.000     0.972       -         
jtag_controller.\$1245_cry_0_0                           CCU2D        S1       Out     1.346     2.318       -         
addr_i[2]                                                Net          -        -       -         -           3         
jtag_controller.\$1074_1_cry_0_0                         CCU2D        A1       In      0.000     2.318       -         
jtag_controller.\$1074_1_cry_0_0                         CCU2D        COUT     Out     1.544     3.862       -         
Z\$1074_1_cry_0                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_1_0                         CCU2D        CIN      In      0.000     3.862       -         
jtag_controller.\$1074_1_cry_1_0                         CCU2D        COUT     Out     0.143     4.005       -         
Z\$1074_1_cry_2                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_3_0                         CCU2D        CIN      In      0.000     4.005       -         
jtag_controller.\$1074_1_cry_3_0                         CCU2D        COUT     Out     0.143     4.148       -         
Z\$1074_1_cry_4                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_5_0                         CCU2D        CIN      In      0.000     4.148       -         
jtag_controller.\$1074_1_cry_5_0                         CCU2D        COUT     Out     0.143     4.291       -         
Z\$1074_1_cry_6                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_7_0                         CCU2D        CIN      In      0.000     4.291       -         
jtag_controller.\$1074_1_cry_7_0                         CCU2D        COUT     Out     0.143     4.434       -         
Z\$1074_1_cry_8                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_9_0                         CCU2D        CIN      In      0.000     4.434       -         
jtag_controller.\$1074_1_cry_9_0                         CCU2D        COUT     Out     0.143     4.576       -         
Z\$1074_1_cry_10                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_11_0                        CCU2D        CIN      In      0.000     4.576       -         
jtag_controller.\$1074_1_cry_11_0                        CCU2D        COUT     Out     0.143     4.719       -         
Z\$1074_1_cry_12                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_13_0                        CCU2D        CIN      In      0.000     4.719       -         
jtag_controller.\$1074_1_cry_13_0                        CCU2D        COUT     Out     0.143     4.862       -         
Z\$1074_1_cry_14                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_15_0                        CCU2D        CIN      In      0.000     4.862       -         
jtag_controller.\$1074_1_cry_15_0                        CCU2D        COUT     Out     0.143     5.005       -         
Z\$1074_1_cry_16                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_17_0                        CCU2D        CIN      In      0.000     5.005       -         
jtag_controller.\$1074_1_cry_17_0                        CCU2D        COUT     Out     0.143     5.147       -         
Z\$1074_1_cry_18                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_19_0                        CCU2D        CIN      In      0.000     5.147       -         
jtag_controller.\$1074_1_cry_19_0                        CCU2D        COUT     Out     0.143     5.290       -         
Z\$1074_1_cry_20                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_21_0                        CCU2D        CIN      In      0.000     5.290       -         
jtag_controller.\$1074_1_cry_21_0                        CCU2D        COUT     Out     0.143     5.433       -         
Z\$1074_1_cry_22                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_23_0                        CCU2D        CIN      In      0.000     5.433       -         
jtag_controller.\$1074_1_cry_23_0                        CCU2D        S0       Out     1.549     6.982       -         
Z\$1074_1[25]                                            Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_15_0_RNITA4E                ORCALUT4     D        In      0.000     6.982       -         
jtag_controller.\$1074_1_cry_15_0_RNITA4E                ORCALUT4     Z        Out     1.017     7.999       -         
data\$next_104_sn_m27_639_i_a2_0_15                      Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_11_0_RNIU7MI1               ORCALUT4     C        In      0.000     7.999       -         
jtag_controller.\$1074_1_cry_11_0_RNIU7MI1               ORCALUT4     Z        Out     1.017     9.016       -         
data\$next_104_sn_m27_639_i_a2_0_25                      Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_27_0_RNIK3JB3               ORCALUT4     D        In      0.000     9.016       -         
jtag_controller.\$1074_1_cry_27_0_RNIK3JB3               ORCALUT4     Z        Out     1.153     10.168      -         
N_123                                                    Net          -        -       -         -           3         
jtag_controller.data\$next_2_sqmuxa_4                    ORCALUT4     D        In      0.000     10.168      -         
jtag_controller.data\$next_2_sqmuxa_4                    ORCALUT4     Z        Out     1.017     11.185      -         
data\$next_2_sqmuxa_4                                    Net          -        -       -         -           1         
jtag_controller.un1_data\$next_2_sqmuxa_9_0              ORCALUT4     A        In      0.000     11.185      -         
jtag_controller.un1_data\$next_2_sqmuxa_9_0              ORCALUT4     Z        Out     1.089     12.274      -         
un1_data\$next_2_sqmuxa_9_0                              Net          -        -       -         -           2         
jtag_controller.un1_data\$next_2_sqmuxa_9_0_RNIP8LUA     ORCALUT4     D        In      0.000     12.274      -         
jtag_controller.un1_data\$next_2_sqmuxa_9_0_RNIP8LUA     ORCALUT4     Z        Out     1.089     13.363      -         
un1_data\$next_2_sqmuxa_9                                Net          -        -       -         -           2         
jtag_controller.un1_data\$next_2_sqmuxa_8_5_RNI349VF     ORCALUT4     D        In      0.000     13.363      -         
jtag_controller.un1_data\$next_2_sqmuxa_8_5_RNI349VF     ORCALUT4     Z        Out     1.364     14.727      -         
un1_data\$next284_i                                      Net          -        -       -         -           32        
jtag_controller.data[0]                                  FD1P3AX      SP       In      0.000     14.727      -         
=======================================================================================================================


Path information for path number 3: 
      Requested Period:                      10.000
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.528

    - Propagation time:                      14.727
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -5.199

    Number of logic level(s):                21
    Starting point:                          jtag_controller.addr_fast[2] / Q
    Ending point:                            jtag_controller.data[31] / SP
    The start point is clocked by            jtag|jtag_clk_inferred_clock [falling] on pin CK
    The end   point is clocked by            jtag|jtag_clk_inferred_clock [falling] on pin CK

Instance / Net                                                        Pin      Pin               Arrival     No. of    
Name                                                     Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------
jtag_controller.addr_fast[2]                             FD1P3AX      Q        Out     0.972     0.972       -         
addr_fast[2]                                             Net          -        -       -         -           1         
jtag_controller.\$1245_cry_0_0                           CCU2D        A1       In      0.000     0.972       -         
jtag_controller.\$1245_cry_0_0                           CCU2D        S1       Out     1.346     2.318       -         
addr_i[2]                                                Net          -        -       -         -           3         
jtag_controller.\$1074_1_cry_0_0                         CCU2D        A1       In      0.000     2.318       -         
jtag_controller.\$1074_1_cry_0_0                         CCU2D        COUT     Out     1.544     3.862       -         
Z\$1074_1_cry_0                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_1_0                         CCU2D        CIN      In      0.000     3.862       -         
jtag_controller.\$1074_1_cry_1_0                         CCU2D        COUT     Out     0.143     4.005       -         
Z\$1074_1_cry_2                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_3_0                         CCU2D        CIN      In      0.000     4.005       -         
jtag_controller.\$1074_1_cry_3_0                         CCU2D        COUT     Out     0.143     4.148       -         
Z\$1074_1_cry_4                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_5_0                         CCU2D        CIN      In      0.000     4.148       -         
jtag_controller.\$1074_1_cry_5_0                         CCU2D        COUT     Out     0.143     4.291       -         
Z\$1074_1_cry_6                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_7_0                         CCU2D        CIN      In      0.000     4.291       -         
jtag_controller.\$1074_1_cry_7_0                         CCU2D        COUT     Out     0.143     4.434       -         
Z\$1074_1_cry_8                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_9_0                         CCU2D        CIN      In      0.000     4.434       -         
jtag_controller.\$1074_1_cry_9_0                         CCU2D        COUT     Out     0.143     4.576       -         
Z\$1074_1_cry_10                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_11_0                        CCU2D        CIN      In      0.000     4.576       -         
jtag_controller.\$1074_1_cry_11_0                        CCU2D        COUT     Out     0.143     4.719       -         
Z\$1074_1_cry_12                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_13_0                        CCU2D        CIN      In      0.000     4.719       -         
jtag_controller.\$1074_1_cry_13_0                        CCU2D        COUT     Out     0.143     4.862       -         
Z\$1074_1_cry_14                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_15_0                        CCU2D        CIN      In      0.000     4.862       -         
jtag_controller.\$1074_1_cry_15_0                        CCU2D        COUT     Out     0.143     5.005       -         
Z\$1074_1_cry_16                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_17_0                        CCU2D        CIN      In      0.000     5.005       -         
jtag_controller.\$1074_1_cry_17_0                        CCU2D        COUT     Out     0.143     5.147       -         
Z\$1074_1_cry_18                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_19_0                        CCU2D        CIN      In      0.000     5.147       -         
jtag_controller.\$1074_1_cry_19_0                        CCU2D        COUT     Out     0.143     5.290       -         
Z\$1074_1_cry_20                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_21_0                        CCU2D        CIN      In      0.000     5.290       -         
jtag_controller.\$1074_1_cry_21_0                        CCU2D        COUT     Out     0.143     5.433       -         
Z\$1074_1_cry_22                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_23_0                        CCU2D        CIN      In      0.000     5.433       -         
jtag_controller.\$1074_1_cry_23_0                        CCU2D        S1       Out     1.549     6.982       -         
Z\$1074_1[26]                                            Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_15_0_RNI1J8E                ORCALUT4     D        In      0.000     6.982       -         
jtag_controller.\$1074_1_cry_15_0_RNI1J8E                ORCALUT4     Z        Out     1.017     7.999       -         
data\$next_104_sn_m27_639_i_a2_0_16                      Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_11_0_RNIU7MI1               ORCALUT4     D        In      0.000     7.999       -         
jtag_controller.\$1074_1_cry_11_0_RNIU7MI1               ORCALUT4     Z        Out     1.017     9.016       -         
data\$next_104_sn_m27_639_i_a2_0_25                      Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_27_0_RNIK3JB3               ORCALUT4     D        In      0.000     9.016       -         
jtag_controller.\$1074_1_cry_27_0_RNIK3JB3               ORCALUT4     Z        Out     1.153     10.168      -         
N_123                                                    Net          -        -       -         -           3         
jtag_controller.data\$next_2_sqmuxa_4                    ORCALUT4     D        In      0.000     10.168      -         
jtag_controller.data\$next_2_sqmuxa_4                    ORCALUT4     Z        Out     1.017     11.185      -         
data\$next_2_sqmuxa_4                                    Net          -        -       -         -           1         
jtag_controller.un1_data\$next_2_sqmuxa_9_0              ORCALUT4     A        In      0.000     11.185      -         
jtag_controller.un1_data\$next_2_sqmuxa_9_0              ORCALUT4     Z        Out     1.089     12.274      -         
un1_data\$next_2_sqmuxa_9_0                              Net          -        -       -         -           2         
jtag_controller.un1_data\$next_2_sqmuxa_9_0_RNIP8LUA     ORCALUT4     D        In      0.000     12.274      -         
jtag_controller.un1_data\$next_2_sqmuxa_9_0_RNIP8LUA     ORCALUT4     Z        Out     1.089     13.363      -         
un1_data\$next_2_sqmuxa_9                                Net          -        -       -         -           2         
jtag_controller.un1_data\$next_2_sqmuxa_8_5_RNI349VF     ORCALUT4     D        In      0.000     13.363      -         
jtag_controller.un1_data\$next_2_sqmuxa_8_5_RNI349VF     ORCALUT4     Z        Out     1.364     14.727      -         
un1_data\$next284_i                                      Net          -        -       -         -           32        
jtag_controller.data[31]                                 FD1P3AX      SP       In      0.000     14.727      -         
=======================================================================================================================


Path information for path number 4: 
      Requested Period:                      10.000
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.528

    - Propagation time:                      14.727
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -5.199

    Number of logic level(s):                21
    Starting point:                          jtag_controller.addr_fast[2] / Q
    Ending point:                            jtag_controller.data[30] / SP
    The start point is clocked by            jtag|jtag_clk_inferred_clock [falling] on pin CK
    The end   point is clocked by            jtag|jtag_clk_inferred_clock [falling] on pin CK

Instance / Net                                                        Pin      Pin               Arrival     No. of    
Name                                                     Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------
jtag_controller.addr_fast[2]                             FD1P3AX      Q        Out     0.972     0.972       -         
addr_fast[2]                                             Net          -        -       -         -           1         
jtag_controller.\$1245_cry_0_0                           CCU2D        A1       In      0.000     0.972       -         
jtag_controller.\$1245_cry_0_0                           CCU2D        S1       Out     1.346     2.318       -         
addr_i[2]                                                Net          -        -       -         -           3         
jtag_controller.\$1074_1_cry_0_0                         CCU2D        A1       In      0.000     2.318       -         
jtag_controller.\$1074_1_cry_0_0                         CCU2D        COUT     Out     1.544     3.862       -         
Z\$1074_1_cry_0                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_1_0                         CCU2D        CIN      In      0.000     3.862       -         
jtag_controller.\$1074_1_cry_1_0                         CCU2D        COUT     Out     0.143     4.005       -         
Z\$1074_1_cry_2                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_3_0                         CCU2D        CIN      In      0.000     4.005       -         
jtag_controller.\$1074_1_cry_3_0                         CCU2D        COUT     Out     0.143     4.148       -         
Z\$1074_1_cry_4                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_5_0                         CCU2D        CIN      In      0.000     4.148       -         
jtag_controller.\$1074_1_cry_5_0                         CCU2D        COUT     Out     0.143     4.291       -         
Z\$1074_1_cry_6                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_7_0                         CCU2D        CIN      In      0.000     4.291       -         
jtag_controller.\$1074_1_cry_7_0                         CCU2D        COUT     Out     0.143     4.434       -         
Z\$1074_1_cry_8                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_9_0                         CCU2D        CIN      In      0.000     4.434       -         
jtag_controller.\$1074_1_cry_9_0                         CCU2D        COUT     Out     0.143     4.576       -         
Z\$1074_1_cry_10                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_11_0                        CCU2D        CIN      In      0.000     4.576       -         
jtag_controller.\$1074_1_cry_11_0                        CCU2D        COUT     Out     0.143     4.719       -         
Z\$1074_1_cry_12                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_13_0                        CCU2D        CIN      In      0.000     4.719       -         
jtag_controller.\$1074_1_cry_13_0                        CCU2D        COUT     Out     0.143     4.862       -         
Z\$1074_1_cry_14                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_15_0                        CCU2D        CIN      In      0.000     4.862       -         
jtag_controller.\$1074_1_cry_15_0                        CCU2D        COUT     Out     0.143     5.005       -         
Z\$1074_1_cry_16                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_17_0                        CCU2D        CIN      In      0.000     5.005       -         
jtag_controller.\$1074_1_cry_17_0                        CCU2D        COUT     Out     0.143     5.147       -         
Z\$1074_1_cry_18                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_19_0                        CCU2D        CIN      In      0.000     5.147       -         
jtag_controller.\$1074_1_cry_19_0                        CCU2D        COUT     Out     0.143     5.290       -         
Z\$1074_1_cry_20                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_21_0                        CCU2D        CIN      In      0.000     5.290       -         
jtag_controller.\$1074_1_cry_21_0                        CCU2D        COUT     Out     0.143     5.433       -         
Z\$1074_1_cry_22                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_23_0                        CCU2D        CIN      In      0.000     5.433       -         
jtag_controller.\$1074_1_cry_23_0                        CCU2D        S1       Out     1.549     6.982       -         
Z\$1074_1[26]                                            Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_15_0_RNI1J8E                ORCALUT4     D        In      0.000     6.982       -         
jtag_controller.\$1074_1_cry_15_0_RNI1J8E                ORCALUT4     Z        Out     1.017     7.999       -         
data\$next_104_sn_m27_639_i_a2_0_16                      Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_11_0_RNIU7MI1               ORCALUT4     D        In      0.000     7.999       -         
jtag_controller.\$1074_1_cry_11_0_RNIU7MI1               ORCALUT4     Z        Out     1.017     9.016       -         
data\$next_104_sn_m27_639_i_a2_0_25                      Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_27_0_RNIK3JB3               ORCALUT4     D        In      0.000     9.016       -         
jtag_controller.\$1074_1_cry_27_0_RNIK3JB3               ORCALUT4     Z        Out     1.153     10.168      -         
N_123                                                    Net          -        -       -         -           3         
jtag_controller.data\$next_2_sqmuxa_4                    ORCALUT4     D        In      0.000     10.168      -         
jtag_controller.data\$next_2_sqmuxa_4                    ORCALUT4     Z        Out     1.017     11.185      -         
data\$next_2_sqmuxa_4                                    Net          -        -       -         -           1         
jtag_controller.un1_data\$next_2_sqmuxa_9_0              ORCALUT4     A        In      0.000     11.185      -         
jtag_controller.un1_data\$next_2_sqmuxa_9_0              ORCALUT4     Z        Out     1.089     12.274      -         
un1_data\$next_2_sqmuxa_9_0                              Net          -        -       -         -           2         
jtag_controller.un1_data\$next_2_sqmuxa_9_0_RNIP8LUA     ORCALUT4     D        In      0.000     12.274      -         
jtag_controller.un1_data\$next_2_sqmuxa_9_0_RNIP8LUA     ORCALUT4     Z        Out     1.089     13.363      -         
un1_data\$next_2_sqmuxa_9                                Net          -        -       -         -           2         
jtag_controller.un1_data\$next_2_sqmuxa_8_5_RNI349VF     ORCALUT4     D        In      0.000     13.363      -         
jtag_controller.un1_data\$next_2_sqmuxa_8_5_RNI349VF     ORCALUT4     Z        Out     1.364     14.727      -         
un1_data\$next284_i                                      Net          -        -       -         -           32        
jtag_controller.data[30]                                 FD1P3AX      SP       In      0.000     14.727      -         
=======================================================================================================================


Path information for path number 5: 
      Requested Period:                      10.000
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.528

    - Propagation time:                      14.727
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -5.199

    Number of logic level(s):                21
    Starting point:                          jtag_controller.addr_fast[2] / Q
    Ending point:                            jtag_controller.data[29] / SP
    The start point is clocked by            jtag|jtag_clk_inferred_clock [falling] on pin CK
    The end   point is clocked by            jtag|jtag_clk_inferred_clock [falling] on pin CK

Instance / Net                                                        Pin      Pin               Arrival     No. of    
Name                                                     Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------
jtag_controller.addr_fast[2]                             FD1P3AX      Q        Out     0.972     0.972       -         
addr_fast[2]                                             Net          -        -       -         -           1         
jtag_controller.\$1245_cry_0_0                           CCU2D        A1       In      0.000     0.972       -         
jtag_controller.\$1245_cry_0_0                           CCU2D        S1       Out     1.346     2.318       -         
addr_i[2]                                                Net          -        -       -         -           3         
jtag_controller.\$1074_1_cry_0_0                         CCU2D        A1       In      0.000     2.318       -         
jtag_controller.\$1074_1_cry_0_0                         CCU2D        COUT     Out     1.544     3.862       -         
Z\$1074_1_cry_0                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_1_0                         CCU2D        CIN      In      0.000     3.862       -         
jtag_controller.\$1074_1_cry_1_0                         CCU2D        COUT     Out     0.143     4.005       -         
Z\$1074_1_cry_2                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_3_0                         CCU2D        CIN      In      0.000     4.005       -         
jtag_controller.\$1074_1_cry_3_0                         CCU2D        COUT     Out     0.143     4.148       -         
Z\$1074_1_cry_4                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_5_0                         CCU2D        CIN      In      0.000     4.148       -         
jtag_controller.\$1074_1_cry_5_0                         CCU2D        COUT     Out     0.143     4.291       -         
Z\$1074_1_cry_6                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_7_0                         CCU2D        CIN      In      0.000     4.291       -         
jtag_controller.\$1074_1_cry_7_0                         CCU2D        COUT     Out     0.143     4.434       -         
Z\$1074_1_cry_8                                          Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_9_0                         CCU2D        CIN      In      0.000     4.434       -         
jtag_controller.\$1074_1_cry_9_0                         CCU2D        COUT     Out     0.143     4.576       -         
Z\$1074_1_cry_10                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_11_0                        CCU2D        CIN      In      0.000     4.576       -         
jtag_controller.\$1074_1_cry_11_0                        CCU2D        COUT     Out     0.143     4.719       -         
Z\$1074_1_cry_12                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_13_0                        CCU2D        CIN      In      0.000     4.719       -         
jtag_controller.\$1074_1_cry_13_0                        CCU2D        COUT     Out     0.143     4.862       -         
Z\$1074_1_cry_14                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_15_0                        CCU2D        CIN      In      0.000     4.862       -         
jtag_controller.\$1074_1_cry_15_0                        CCU2D        COUT     Out     0.143     5.005       -         
Z\$1074_1_cry_16                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_17_0                        CCU2D        CIN      In      0.000     5.005       -         
jtag_controller.\$1074_1_cry_17_0                        CCU2D        COUT     Out     0.143     5.147       -         
Z\$1074_1_cry_18                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_19_0                        CCU2D        CIN      In      0.000     5.147       -         
jtag_controller.\$1074_1_cry_19_0                        CCU2D        COUT     Out     0.143     5.290       -         
Z\$1074_1_cry_20                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_21_0                        CCU2D        CIN      In      0.000     5.290       -         
jtag_controller.\$1074_1_cry_21_0                        CCU2D        COUT     Out     0.143     5.433       -         
Z\$1074_1_cry_22                                         Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_23_0                        CCU2D        CIN      In      0.000     5.433       -         
jtag_controller.\$1074_1_cry_23_0                        CCU2D        S1       Out     1.549     6.982       -         
Z\$1074_1[26]                                            Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_15_0_RNI1J8E                ORCALUT4     D        In      0.000     6.982       -         
jtag_controller.\$1074_1_cry_15_0_RNI1J8E                ORCALUT4     Z        Out     1.017     7.999       -         
data\$next_104_sn_m27_639_i_a2_0_16                      Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_11_0_RNIU7MI1               ORCALUT4     D        In      0.000     7.999       -         
jtag_controller.\$1074_1_cry_11_0_RNIU7MI1               ORCALUT4     Z        Out     1.017     9.016       -         
data\$next_104_sn_m27_639_i_a2_0_25                      Net          -        -       -         -           1         
jtag_controller.\$1074_1_cry_27_0_RNIK3JB3               ORCALUT4     D        In      0.000     9.016       -         
jtag_controller.\$1074_1_cry_27_0_RNIK3JB3               ORCALUT4     Z        Out     1.153     10.168      -         
N_123                                                    Net          -        -       -         -           3         
jtag_controller.data\$next_2_sqmuxa_4                    ORCALUT4     D        In      0.000     10.168      -         
jtag_controller.data\$next_2_sqmuxa_4                    ORCALUT4     Z        Out     1.017     11.185      -         
data\$next_2_sqmuxa_4                                    Net          -        -       -         -           1         
jtag_controller.un1_data\$next_2_sqmuxa_9_0              ORCALUT4     A        In      0.000     11.185      -         
jtag_controller.un1_data\$next_2_sqmuxa_9_0              ORCALUT4     Z        Out     1.089     12.274      -         
un1_data\$next_2_sqmuxa_9_0                              Net          -        -       -         -           2         
jtag_controller.un1_data\$next_2_sqmuxa_9_0_RNIP8LUA     ORCALUT4     D        In      0.000     12.274      -         
jtag_controller.un1_data\$next_2_sqmuxa_9_0_RNIP8LUA     ORCALUT4     Z        Out     1.089     13.363      -         
un1_data\$next_2_sqmuxa_9                                Net          -        -       -         -           2         
jtag_controller.un1_data\$next_2_sqmuxa_8_5_RNI349VF     ORCALUT4     D        In      0.000     13.363      -         
jtag_controller.un1_data\$next_2_sqmuxa_8_5_RNI349VF     ORCALUT4     Z        Out     1.364     14.727      -         
un1_data\$next284_i                                      Net          -        -       -         -           32        
jtag_controller.data[29]                                 FD1P3AX      SP       In      0.000     14.727      -         
=======================================================================================================================




====================================
Detailed Report for Clock: pll|plugin_ddr_clk_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                   Starting                                                                             Arrival          
Instance                           Reference                             Type        Pin     Net                        Time        Slack
                                   Clock                                                                                                 
-----------------------------------------------------------------------------------------------------------------------------------------
clocking.plugin_ddr.counter[0]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     Q       clocking_counter\$3[0]     1.108       3.551
clocking.plugin_ddr.counter[1]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     Q       clocking_counter\$3[1]     1.044       3.758
clocking.plugin_ddr.counter[2]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     Q       clocking_counter\$3[2]     1.044       3.758
clocking.plugin_ddr.counter[3]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     Q       clocking_counter\$3[3]     1.044       3.901
clocking.plugin_ddr.counter[4]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     Q       clocking_counter\$3[4]     1.044       3.901
clocking.plugin_ddr.counter[5]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     Q       clocking_counter\$3[5]     1.044       4.043
clocking.plugin_ddr.counter[6]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     Q       clocking_counter\$3[6]     1.044       4.043
clocking.plugin_ddr.counter[7]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     Q       clocking_counter\$3[7]     1.044       4.186
clocking.plugin_ddr.counter[8]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     Q       clocking_counter\$3[8]     1.044       4.186
clocking.plugin_ddr.counter[9]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     Q       clocking_counter\$3[9]     1.044       4.329
=========================================================================================================================================


Ending Points with Worst Slack
******************************

                                    Starting                                                               Required          
Instance                            Reference                             Type        Pin     Net          Time         Slack
                                    Clock                                                                                    
-----------------------------------------------------------------------------------------------------------------------------
clocking.plugin_ddr.counter[31]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     D       Z\$2[31]     9.894        3.551
clocking.plugin_ddr.counter[29]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     D       Z\$2[29]     9.894        3.694
clocking.plugin_ddr.counter[30]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     D       Z\$2[30]     9.894        3.694
clocking.plugin_ddr.counter[27]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     D       Z\$2[27]     9.894        3.837
clocking.plugin_ddr.counter[28]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     D       Z\$2[28]     9.894        3.837
clocking.plugin_ddr.counter[25]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     D       Z\$2[25]     9.894        3.979
clocking.plugin_ddr.counter[26]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     D       Z\$2[26]     9.894        3.979
clocking.plugin_ddr.counter[23]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     D       Z\$2[23]     9.894        4.122
clocking.plugin_ddr.counter[24]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     D       Z\$2[24]     9.894        4.122
clocking.plugin_ddr.counter[21]     pll|plugin_ddr_clk_inferred_clock     FD1S3IX     D       Z\$2[21]     9.894        4.265
=============================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.894

    - Propagation time:                      6.343
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 3.551

    Number of logic level(s):                17
    Starting point:                          clocking.plugin_ddr.counter[0] / Q
    Ending point:                            clocking.plugin_ddr.counter[31] / D
    The start point is clocked by            pll|plugin_ddr_clk_inferred_clock [rising] on pin CK
    The end   point is clocked by            pll|plugin_ddr_clk_inferred_clock [rising] on pin CK

Instance / Net                                   Pin      Pin               Arrival     No. of    
Name                                 Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------
clocking.plugin_ddr.counter[0]       FD1S3IX     Q        Out     1.108     1.108       -         
clocking_counter\$3[0]               Net         -        -       -         -           3         
clocking.plugin_ddr.\$2_cry_0_0      CCU2D       A1       In      0.000     1.108       -         
clocking.plugin_ddr.\$2_cry_0_0      CCU2D       COUT     Out     1.544     2.652       -         
Z\$2_cry_0                           Net         -        -       -         -           1         
clocking.plugin_ddr.\$2_cry_1_0      CCU2D       CIN      In      0.000     2.652       -         
clocking.plugin_ddr.\$2_cry_1_0      CCU2D       COUT     Out     0.143     2.795       -         
Z\$2_cry_2                           Net         -        -       -         -           1         
clocking.plugin_ddr.\$2_cry_3_0      CCU2D       CIN      In      0.000     2.795       -         
clocking.plugin_ddr.\$2_cry_3_0      CCU2D       COUT     Out     0.143     2.938       -         
Z\$2_cry_4                           Net         -        -       -         -           1         
clocking.plugin_ddr.\$2_cry_5_0      CCU2D       CIN      In      0.000     2.938       -         
clocking.plugin_ddr.\$2_cry_5_0      CCU2D       COUT     Out     0.143     3.081       -         
Z\$2_cry_6                           Net         -        -       -         -           1         
clocking.plugin_ddr.\$2_cry_7_0      CCU2D       CIN      In      0.000     3.081       -         
clocking.plugin_ddr.\$2_cry_7_0      CCU2D       COUT     Out     0.143     3.224       -         
Z\$2_cry_8                           Net         -        -       -         -           1         
clocking.plugin_ddr.\$2_cry_9_0      CCU2D       CIN      In      0.000     3.224       -         
clocking.plugin_ddr.\$2_cry_9_0      CCU2D       COUT     Out     0.143     3.366       -         
Z\$2_cry_10                          Net         -        -       -         -           1         
clocking.plugin_ddr.\$2_cry_11_0     CCU2D       CIN      In      0.000     3.366       -         
clocking.plugin_ddr.\$2_cry_11_0     CCU2D       COUT     Out     0.143     3.509       -         
Z\$2_cry_12                          Net         -        -       -         -           1         
clocking.plugin_ddr.\$2_cry_13_0     CCU2D       CIN      In      0.000     3.509       -         
clocking.plugin_ddr.\$2_cry_13_0     CCU2D       COUT     Out     0.143     3.652       -         
Z\$2_cry_14                          Net         -        -       -         -           1         
clocking.plugin_ddr.\$2_cry_15_0     CCU2D       CIN      In      0.000     3.652       -         
clocking.plugin_ddr.\$2_cry_15_0     CCU2D       COUT     Out     0.143     3.795       -         
Z\$2_cry_16                          Net         -        -       -         -           1         
clocking.plugin_ddr.\$2_cry_17_0     CCU2D       CIN      In      0.000     3.795       -         
clocking.plugin_ddr.\$2_cry_17_0     CCU2D       COUT     Out     0.143     3.938       -         
Z\$2_cry_18                          Net         -        -       -         -           1         
clocking.plugin_ddr.\$2_cry_19_0     CCU2D       CIN      In      0.000     3.938       -         
clocking.plugin_ddr.\$2_cry_19_0     CCU2D       COUT     Out     0.143     4.080       -         
Z\$2_cry_20                          Net         -        -       -         -           1         
clocking.plugin_ddr.\$2_cry_21_0     CCU2D       CIN      In      0.000     4.080       -         
clocking.plugin_ddr.\$2_cry_21_0     CCU2D       COUT     Out     0.143     4.223       -         
Z\$2_cry_22                          Net         -        -       -         -           1         
clocking.plugin_ddr.\$2_cry_23_0     CCU2D       CIN      In      0.000     4.223       -         
clocking.plugin_ddr.\$2_cry_23_0     CCU2D       COUT     Out     0.143     4.366       -         
Z\$2_cry_24                          Net         -        -       -         -           1         
clocking.plugin_ddr.\$2_cry_25_0     CCU2D       CIN      In      0.000     4.366       -         
clocking.plugin_ddr.\$2_cry_25_0     CCU2D       COUT     Out     0.143     4.509       -         
Z\$2_cry_26                          Net         -        -       -         -           1         
clocking.plugin_ddr.\$2_cry_27_0     CCU2D       CIN      In      0.000     4.509       -         
clocking.plugin_ddr.\$2_cry_27_0     CCU2D       COUT     Out     0.143     4.652       -         
Z\$2_cry_28                          Net         -        -       -         -           1         
clocking.plugin_ddr.\$2_cry_29_0     CCU2D       CIN      In      0.000     4.652       -         
clocking.plugin_ddr.\$2_cry_29_0     CCU2D       COUT     Out     0.143     4.794       -         
Z\$2_cry_30                          Net         -        -       -         -           1         
clocking.plugin_ddr.\$2_s_31_0       CCU2D       CIN      In      0.000     4.794       -         
clocking.plugin_ddr.\$2_s_31_0       CCU2D       S0       Out     1.549     6.343       -         
Z\$2[31]                             Net         -        -       -         -           1         
clocking.plugin_ddr.counter[31]      FD1S3IX     D        In      0.000     6.343       -         
==================================================================================================




====================================
Detailed Report for Clock: plugin_stream_input_0__clk_word__p
====================================



Starting Points with Worst Slack
********************************

                                  Starting                                                                              Arrival           
Instance                          Reference                              Type        Pin     Net                        Time        Slack 
                                  Clock                                                                                                   
------------------------------------------------------------------------------------------------------------------------------------------
clocking.plugin_in.counter[0]     plugin_stream_input_0__clk_word__p     FD1S3AX     Q       clocking_counter\$1[0]     1.044       13.615
clocking.plugin_in.counter[1]     plugin_stream_input_0__clk_word__p     FD1S3AX     Q       clocking_counter\$1[1]     1.044       13.758
clocking.plugin_in.counter[2]     plugin_stream_input_0__clk_word__p     FD1S3AX     Q       clocking_counter\$1[2]     1.044       13.758
clocking.plugin_in.counter[3]     plugin_stream_input_0__clk_word__p     FD1S3AX     Q       clocking_counter\$1[3]     1.044       13.901
clocking.plugin_in.counter[4]     plugin_stream_input_0__clk_word__p     FD1S3AX     Q       clocking_counter\$1[4]     1.044       13.901
clocking.plugin_in.counter[5]     plugin_stream_input_0__clk_word__p     FD1S3AX     Q       clocking_counter\$1[5]     1.044       14.043
clocking.plugin_in.counter[6]     plugin_stream_input_0__clk_word__p     FD1S3AX     Q       clocking_counter\$1[6]     1.044       14.043
clocking.plugin_in.counter[7]     plugin_stream_input_0__clk_word__p     FD1S3AX     Q       clocking_counter\$1[7]     1.044       14.186
clocking.plugin_in.counter[8]     plugin_stream_input_0__clk_word__p     FD1S3AX     Q       clocking_counter\$1[8]     1.044       14.186
clocking.plugin_in.counter[9]     plugin_stream_input_0__clk_word__p     FD1S3AX     Q       clocking_counter\$1[9]     1.044       14.329
==========================================================================================================================================


Ending Points with Worst Slack
******************************

                                   Starting                                                                     Required           
Instance                           Reference                              Type        Pin     Net               Time         Slack 
                                   Clock                                                                                           
-----------------------------------------------------------------------------------------------------------------------------------
clocking.plugin_in.counter[31]     plugin_stream_input_0__clk_word__p     FD1S3AX     D       counter_s[31]     19.894       13.615
clocking.plugin_in.counter[29]     plugin_stream_input_0__clk_word__p     FD1S3AX     D       counter_s[29]     19.894       13.758
clocking.plugin_in.counter[30]     plugin_stream_input_0__clk_word__p     FD1S3AX     D       counter_s[30]     19.894       13.758
clocking.plugin_in.counter[27]     plugin_stream_input_0__clk_word__p     FD1S3AX     D       counter_s[27]     19.894       13.901
clocking.plugin_in.counter[28]     plugin_stream_input_0__clk_word__p     FD1S3AX     D       counter_s[28]     19.894       13.901
clocking.plugin_in.counter[25]     plugin_stream_input_0__clk_word__p     FD1S3AX     D       counter_s[25]     19.894       14.043
clocking.plugin_in.counter[26]     plugin_stream_input_0__clk_word__p     FD1S3AX     D       counter_s[26]     19.894       14.043
clocking.plugin_in.counter[23]     plugin_stream_input_0__clk_word__p     FD1S3AX     D       counter_s[23]     19.894       14.186
clocking.plugin_in.counter[24]     plugin_stream_input_0__clk_word__p     FD1S3AX     D       counter_s[24]     19.894       14.186
clocking.plugin_in.counter[21]     plugin_stream_input_0__clk_word__p     FD1S3AX     D       counter_s[21]     19.894       14.329
===================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      20.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         19.894

    - Propagation time:                      6.279
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 13.615

    Number of logic level(s):                17
    Starting point:                          clocking.plugin_in.counter[0] / Q
    Ending point:                            clocking.plugin_in.counter[31] / D
    The start point is clocked by            plugin_stream_input_0__clk_word__p [rising] on pin CK
    The end   point is clocked by            plugin_stream_input_0__clk_word__p [rising] on pin CK

Instance / Net                                       Pin      Pin               Arrival     No. of    
Name                                     Type        Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------
clocking.plugin_in.counter[0]            FD1S3AX     Q        Out     1.044     1.044       -         
clocking_counter\$1[0]                   Net         -        -       -         -           2         
clocking.plugin_in.counter_cry_0[0]      CCU2D       A1       In      0.000     1.044       -         
clocking.plugin_in.counter_cry_0[0]      CCU2D       COUT     Out     1.544     2.588       -         
counter_cry[0]                           Net         -        -       -         -           1         
clocking.plugin_in.counter_cry_0[1]      CCU2D       CIN      In      0.000     2.588       -         
clocking.plugin_in.counter_cry_0[1]      CCU2D       COUT     Out     0.143     2.731       -         
counter_cry[2]                           Net         -        -       -         -           1         
clocking.plugin_in.counter_cry_0[3]      CCU2D       CIN      In      0.000     2.731       -         
clocking.plugin_in.counter_cry_0[3]      CCU2D       COUT     Out     0.143     2.874       -         
counter_cry[4]                           Net         -        -       -         -           1         
clocking.plugin_in.counter_cry_0[5]      CCU2D       CIN      In      0.000     2.874       -         
clocking.plugin_in.counter_cry_0[5]      CCU2D       COUT     Out     0.143     3.017       -         
counter_cry[6]                           Net         -        -       -         -           1         
clocking.plugin_in.counter_cry_0[7]      CCU2D       CIN      In      0.000     3.017       -         
clocking.plugin_in.counter_cry_0[7]      CCU2D       COUT     Out     0.143     3.159       -         
counter_cry[8]                           Net         -        -       -         -           1         
clocking.plugin_in.counter_cry_0[9]      CCU2D       CIN      In      0.000     3.159       -         
clocking.plugin_in.counter_cry_0[9]      CCU2D       COUT     Out     0.143     3.302       -         
counter_cry[10]                          Net         -        -       -         -           1         
clocking.plugin_in.counter_cry_0[11]     CCU2D       CIN      In      0.000     3.302       -         
clocking.plugin_in.counter_cry_0[11]     CCU2D       COUT     Out     0.143     3.445       -         
counter_cry[12]                          Net         -        -       -         -           1         
clocking.plugin_in.counter_cry_0[13]     CCU2D       CIN      In      0.000     3.445       -         
clocking.plugin_in.counter_cry_0[13]     CCU2D       COUT     Out     0.143     3.588       -         
counter_cry[14]                          Net         -        -       -         -           1         
clocking.plugin_in.counter_cry_0[15]     CCU2D       CIN      In      0.000     3.588       -         
clocking.plugin_in.counter_cry_0[15]     CCU2D       COUT     Out     0.143     3.731       -         
counter_cry[16]                          Net         -        -       -         -           1         
clocking.plugin_in.counter_cry_0[17]     CCU2D       CIN      In      0.000     3.731       -         
clocking.plugin_in.counter_cry_0[17]     CCU2D       COUT     Out     0.143     3.873       -         
counter_cry[18]                          Net         -        -       -         -           1         
clocking.plugin_in.counter_cry_0[19]     CCU2D       CIN      In      0.000     3.873       -         
clocking.plugin_in.counter_cry_0[19]     CCU2D       COUT     Out     0.143     4.016       -         
counter_cry[20]                          Net         -        -       -         -           1         
clocking.plugin_in.counter_cry_0[21]     CCU2D       CIN      In      0.000     4.016       -         
clocking.plugin_in.counter_cry_0[21]     CCU2D       COUT     Out     0.143     4.159       -         
counter_cry[22]                          Net         -        -       -         -           1         
clocking.plugin_in.counter_cry_0[23]     CCU2D       CIN      In      0.000     4.159       -         
clocking.plugin_in.counter_cry_0[23]     CCU2D       COUT     Out     0.143     4.302       -         
counter_cry[24]                          Net         -        -       -         -           1         
clocking.plugin_in.counter_cry_0[25]     CCU2D       CIN      In      0.000     4.302       -         
clocking.plugin_in.counter_cry_0[25]     CCU2D       COUT     Out     0.143     4.445       -         
counter_cry[26]                          Net         -        -       -         -           1         
clocking.plugin_in.counter_cry_0[27]     CCU2D       CIN      In      0.000     4.445       -         
clocking.plugin_in.counter_cry_0[27]     CCU2D       COUT     Out     0.143     4.588       -         
counter_cry[28]                          Net         -        -       -         -           1         
clocking.plugin_in.counter_cry_0[29]     CCU2D       CIN      In      0.000     4.588       -         
clocking.plugin_in.counter_cry_0[29]     CCU2D       COUT     Out     0.143     4.730       -         
counter_cry[30]                          Net         -        -       -         -           1         
clocking.plugin_in.counter_s_0[31]       CCU2D       CIN      In      0.000     4.730       -         
clocking.plugin_in.counter_s_0[31]       CCU2D       S0       Out     1.549     6.279       -         
counter_s[31]                            Net         -        -       -         -           1         
clocking.plugin_in.counter[31]           FD1S3AX     D        In      0.000     6.279       -         
======================================================================================================




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                        Starting                                                                 Arrival           
Instance                                Reference     Type          Pin         Net                              Time        Slack 
                                        Clock                                                                                      
-----------------------------------------------------------------------------------------------------------------------------------
jtag_controller.jtag.jtag_primitive     System        JTAGF         JTDI        jtag_tdi                         0.000       5.229 
jtag_controller.jtag.jtag_primitive     System        JTAGF         JSHIFT      jtag_shift_tdo                   0.000       6.422 
rx.pll.inst                             System        EHXPLLJ       INTLOCK     rx_intlock                       0.000       7.224 
rx.pll.inst                             System        EHXPLLJ       LOCK        rx_locked                        0.000       7.224 
rx.pll.inst                             System        EHXPLLJ       CLKOP       clkop                            0.000       10.000
rx.eclk_ddr.inst                        System        ECLKSYNCA     ECLKO       eclk_ddr_plugin_ddr_eclk_clk     0.000       10.000
===================================================================================================================================


Ending Points with Worst Slack
******************************

                                 Starting                                                Required          
Instance                         Reference     Type        Pin     Net                   Time         Slack
                                 Clock                                                                     
-----------------------------------------------------------------------------------------------------------
jtag_controller.fsm_state[1]     System        FD1P3AX     D       N_927                 10.089       5.229
jtag_controller.fsm_state[2]     System        FD1P3AX     D       N_1197_i              10.089       5.333
jtag_controller.fsm_state[0]     System        FD1P3AX     D       N_884                 10.089       6.246
jtag_controller.fsm_state[5]     System        FD1P3AX     D       N_1019_i              10.089       6.422
jtag_controller.data[0]          System        FD1P3AX     D       data\$next_104[0]     10.089       7.224
jtag_controller.data[1]          System        FD1P3AX     D       data\$next_104[1]     10.089       7.438
jtag_controller.data[2]          System        FD1P3AX     D       data\$next_104[2]     10.089       7.438
jtag_controller.data[3]          System        FD1P3AX     D       data\$next_104[3]     10.089       7.438
jtag_controller.data[4]          System        FD1P3AX     D       data\$next_104[4]     10.089       7.438
jtag_controller.fsm_state[6]     System        FD1P3AX     D       fsm_state_RNO[6]      10.089       8.006
===========================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.089

    - Propagation time:                      4.860
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 5.229

    Number of logic level(s):                5
    Starting point:                          jtag_controller.jtag.jtag_primitive / JTDI
    Ending point:                            jtag_controller.fsm_state[1] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            jtag|jtag_clk_inferred_clock [falling] on pin CK

Instance / Net                                          Pin      Pin               Arrival     No. of    
Name                                       Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------
jtag_controller.jtag.jtag_primitive        JTAGF        JTDI     Out     0.000     0.000       -         
jtag_tdi                                   Net          -        -       -         -           78        
jtag_controller.fsm_state_RNIK16N_0[6]     ORCALUT4     B        In      0.000     0.000       -         
jtag_controller.fsm_state_RNIK16N_0[6]     ORCALUT4     Z        Out     1.193     1.193       -         
N_1242                                     Net          -        -       -         -           4         
jtag_controller.fsm_state_RNO_13[1]        ORCALUT4     B        In      0.000     1.193       -         
jtag_controller.fsm_state_RNO_13[1]        ORCALUT4     Z        Out     1.017     2.210       -         
fsm_state\$next_115_4_442_0_0              Net          -        -       -         -           1         
jtag_controller.fsm_state_RNO_7[1]         ORCALUT4     B        In      0.000     2.210       -         
jtag_controller.fsm_state_RNO_7[1]         ORCALUT4     Z        Out     1.017     3.226       -         
fsm_state\$next_115_4_442_0_4              Net          -        -       -         -           1         
jtag_controller.fsm_state_RNO_2[1]         ORCALUT4     D        In      0.000     3.226       -         
jtag_controller.fsm_state_RNO_2[1]         ORCALUT4     Z        Out     1.017     4.243       -         
fsm_state\$next_115_4_442_0_7              Net          -        -       -         -           1         
jtag_controller.fsm_state_RNO[1]           ORCALUT4     C        In      0.000     4.243       -         
jtag_controller.fsm_state_RNO[1]           ORCALUT4     Z        Out     0.617     4.860       -         
N_927                                      Net          -        -       -         -           1         
jtag_controller.fsm_state[1]               FD1P3AX      D        In      0.000     4.860       -         
=========================================================================================================



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 199MB peak: 202MB)


Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 199MB peak: 202MB)

---------------------------------------
Resource Usage Report
Part: lcmxo2_2000hc-6

Register bits: 400 of 2112 (19%)
PIC Latch:       0
I/O cells:       49
Block Rams : 8 of 8 (100%)


Details:
BB:             39
CCU2D:          305
CLKDIVC:        1
DP8KC:          8
ECLKSYNCA:      1
EHXPLLJ:        1
FD1P3AX:        78
FD1S3AX:        234
FD1S3AY:        2
FD1S3BX:        2
FD1S3IX:        84
GSR:            1
IB:             4
INV:            7
JTAGF:          1
L6MUX21:        4
OB:             6
ORCALUT4:       762
PFUMX:          51
PUR:            1
VHI:            27
VLO:            29
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 39MB peak: 202MB)

Process took 0h:00m:07s realtime, 0h:00m:07s cputime
# Thu Nov 19 13:14:20 2020

###########################################################]